Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 3

link to page 3 link to page 1 link to page 4 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 GENERAL DESCRIPTION The ADSP-BF60x processors are members of the Blackfin
Table 1. Processor Comparison (Continued)
family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine
606 607 608 609
a dual-MAC state-of-the-art signal processing engine, the
F F F F
advantages of a clean, orthogonal RISC-like microprocessor
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instruction set, and single-instruction, multiple-data (SIMD)
Processor Feature
multimedia capabilities into a single instruction-set
ADSP ADSP ADSP ADSP
) architecture. re L1 Instruction SRAM 64K o The processors offer performance up to 500 MHz, as well as low L1 Instruction SRAM/Cache 16K static power consumption. Produced with a low-power and low- , per c L1 Data SRAM 32K voltage design methodology, they provide world-class power tes L1 Data SRAM/Cache 32K y management and performance. (b L1 Scratchpad 4K y By integrating a rich set of industry-leading system peripherals L2 Data SRAM 128K 256K and memory (shown in Table 1), Blackfin processors are the L2 Boot ROM 32K platform of choice for next-generation applications that require Memor RISC-like programmability, multimedia support, and leading- Maximum Speed Grade (MHz)2 400 500 edge signal processing in one integrated package. These applica- Maximum SYSCLK (MHz) tions span a wide array of markets, from automotive systems to 250 embedded industrial, instrumentation and power/motor con- Package Options 349-Ball CSP_BGA trol applications. 1 VGA is 640 × 480 pixels per frame. HD is 1280 × 960 pixels per frame. 2
Table 1. Processor Comparison
Maximum speed grade is not available with every possible SYSCLK selection.
6 7 8 9 BLACKFIN PROCESSOR CORE 60 60 60 60 F F F F
As shown in Figure 1, the processor integrates two Blackfin pro-
-B -B -B -B
cessor cores. Each core, shown in Figure 2, contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four
Processor Feature ADSP ADSP ADSP ADSP
video ALUs, and a 40-bit shifter. The computation units process Up/Down/Rotary Counters 1 8-, 16-, or 32-bit data from the register file. Timer/Counters with PWM 8 The compute register file contains eight 32-bit registers. When 3-Phase PWM Units (4-pair) 2 performing compute operations on 16-bit operand data, the SPORTs 3 register file operates as 16 independent 16-bit registers. All SPIs 2 operands for compute operations come from the multiported USB OTG 1 register file and instruction constant fields. Parallel Peripheral Interface 3 Each MAC can perform a 16-bit by 16-bit multiply in each Removable Storage Interface 1 cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation CAN 1 are supported. TWI 2 The ALUs perform a traditional set of arithmetic and logical UART 2 operations on 16-bit or 32-bit data. In addition, many special ADC Control Module (ACM) 1 instructions are included to accelerate various signal processing Link Ports 4 tasks. These include bit operations such as field extract and pop- Ethernet MAC (IEEE 1588) 2 ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video Pixel Compositor (PIXC) No 1 1 instructions include byte alignment and packing operations, Pipelined Vision Processor 16-bit and 8-bit adds with clipping, 8-bit average operations, (PVP) Video Resolution1 No VGA HD and 8-bit subtract/absolute value/accumulate (SAA) operations. Maximum PVP Line Buffer Size N/A 640 1280 Also provided are the compare/select and vector search GPIOs 112 instructions. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible. Rev. A | Page 3 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide