Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Blackfin Dual Core Embedded Processor |
| Pages / Page | 112 / 5 — CRC Protection. PROCESSOR INFRASTRUCTURE. DMA Controllers |
| Revision | A |
| File Format / Size | PDF / 3.4 Mb |
| Document Language | English |
CRC Protection. PROCESSOR INFRASTRUCTURE. DMA Controllers
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Text Version of Document
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 a very small final memory size. The instruction set also provides sequence. Descriptor-based DMA transfers allow multiple fully featured multifunction instructions that allow the pro- DMA sequences to be chained together and a DMA channel can grammer to use many of the processor core resources in a single be programmed to automatically set up and start another DMA instruction. Coupled with many features more often seen on transfer after the current sequence completes. microcontrollers, this instruction set is very efficient when com- The DMA controller supports the following DMA operations. piling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor • A single linear buffer that stops on completion. (O/S kernel, device drivers, debuggers, ISRs) modes of opera- • A linear buffer with negative, positive or zero stride length. tion, allowing multiple levels of access to core • A circular, auto-refreshing buffer that interrupts when each processor resources. buffer becomes full. The assembly language, which takes advantage of the proces- • A similar buffer that interrupts on fractional buffers (for sor’s unique architecture, offers the following advantages: example, 1/2, 1/4). • Seamlessly integrated DSP/MCU features are optimized for • 1D DMA – uses a set of identical ping-pong buffers defined both 8-bit and 16-bit operations. by a linked ring of two-word descriptor sets, each contain- • A multi-issue load/store modified-Harvard architecture, ing a link pointer and an address. which supports two 16-bit MAC or four 8-bit ALU + two • 1D DMA – uses a linked list of 4 word descriptor sets con- load/store + two pointer updates per cycle. taining a link pointer, an address, a length, and a • All registers, I/O, and memory are mapped into a unified configuration. 4G byte memory space, providing a simplified program- • 2D DMA – uses an array of one-word descriptor sets, spec- ming model. ifying only the base DMA address. • Control of all asynchronous and synchronous events to the • 2D DMA – uses a linked list of multi-word descriptor sets, processor is handled by two subsystems: the Core Event specifying everything. Controller (CEC) and the System Event Controller (SEC). • Microcontroller features, such as arbitrary bit and bit-field
CRC Protection
manipulation, insertion, and extraction; integer operations The two CRC protection modules allow system software to peri- on 8-, 16-, and 32-bit data-types; and separate user and odically calculate the signature of code and/or data in memory, supervisor stack pointers. the content of memory-mapped registers, or communication • Code density enhancements, which include intermixing of message objects. Dedicated hardware circuitry compares the 16-bit and 32-bit instructions (no mode switching, no code signature with pre calculated values and triggers appropriate segregation). Frequently used instructions are encoded fault events. in 16 bits. For example, every 100 ms the system software might initiate the signature calculation of the entire memory contents and
PROCESSOR INFRASTRUCTURE
compare these contents with expected, pre calculated values. If a The following sections provide information on the primary mismatch occurs, a fault condition can be generated (via the infrastructure components of the ADSP-BF609 processor. processor core or the trigger routing unit).
DMA Controllers
The CRC is a hardware module based on a CRC32 engine that computes the CRC value of the 32-bit data words presented to The processor uses Direct Memory Access (DMA) to transfer it. Data is provided by the source channel of the memory-to- data within memory spaces or between a memory space and a memory DMA (in memory scan mode) and is optionally for- peripheral. The processor can specify data transfer operations warded to the destination channel (memory transfer mode). and return to normal processing while the fully integrated DMA The main features of the CRC peripheral are: controller carries out the data transfers independent of proces- sor activity. • Memory scan mode DMA transfers can occur between memory and a peripheral or • Memory transfer mode between one memory and another memory. Each Memory-to- • Data verify mode memory DMA stream uses two channels, where one channel is • Data fill mode the source channel, and the second is the destination channel. • User-programmable CRC32 polynomial All DMAs can transport data to and from all on-chip and off- chip memories. Programs can use two types of DMA transfers, • Bit/byte mirroring option (endianness) descriptor-based or register-based. Register-based DMA allows • Fault/error interrupt mechanisms the processor to directly program DMA control registers to ini- • 1D and 2D fill block to initialize array with constants. tiate a DMA transfer. On completion, the control registers may be automatically updated with their original setup values for • 32-bit CRC signature of a block of a memory or MMR continuous transfer. Descriptor-based DMA transfers require a block. set of parameters stored within memory to initiate a DMA Rev. A | Page 5 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
CRC Protection
manipulation, insertion, and extraction; integer operations The two CRC protection modules allow system software to peri- on 8-, 16-, and 32-bit data-types; and separate user and odically calculate the signature of code and/or data in memory, supervisor stack pointers. the content of memory-mapped registers, or communication • Code density enhancements, which include intermixing of message objects. Dedicated hardware circuitry compares the 16-bit and 32-bit instructions (no mode switching, no code signature with pre calculated values and triggers appropriate segregation). Frequently used instructions are encoded fault events. in 16 bits. For example, every 100 ms the system software might initiate the signature calculation of the entire memory contents and
PROCESSOR INFRASTRUCTURE
compare these contents with expected, pre calculated values. If a The following sections provide information on the primary mismatch occurs, a fault condition can be generated (via the infrastructure components of the ADSP-BF609 processor. processor core or the trigger routing unit).
DMA Controllers
The CRC is a hardware module based on a CRC32 engine that computes the CRC value of the 32-bit data words presented to The processor uses Direct Memory Access (DMA) to transfer it. Data is provided by the source channel of the memory-to- data within memory spaces or between a memory space and a memory DMA (in memory scan mode) and is optionally for- peripheral. The processor can specify data transfer operations warded to the destination channel (memory transfer mode). and return to normal processing while the fully integrated DMA The main features of the CRC peripheral are: controller carries out the data transfers independent of proces- sor activity. • Memory scan mode DMA transfers can occur between memory and a peripheral or • Memory transfer mode between one memory and another memory. Each Memory-to- • Data verify mode memory DMA stream uses two channels, where one channel is • Data fill mode the source channel, and the second is the destination channel. • User-programmable CRC32 polynomial All DMAs can transport data to and from all on-chip and off- chip memories. Programs can use two types of DMA transfers, • Bit/byte mirroring option (endianness) descriptor-based or register-based. Register-based DMA allows • Fault/error interrupt mechanisms the processor to directly program DMA control registers to ini- • 1D and 2D fill block to initialize array with constants. tiate a DMA transfer. On completion, the control registers may be automatically updated with their original setup values for • 32-bit CRC signature of a block of a memory or MMR continuous transfer. Descriptor-based DMA transfers require a block. set of parameters stored within memory to initiate a DMA Rev. A | Page 5 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
