Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 6

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Event Handling
operation. Six system-level interrupt channels (PINT0–5) are reserved for this purpose. Each of these interrupt channels can The processor provides event handling that supports both nest- manage up to 32 interrupt pins. The assignment from pin to ing and prioritization. Nesting allows multiple event service interrupt is not performed on a pin-by-pin basis. Rather, groups routines to be active simultaneously. Prioritization ensures that of eight pins (half ports) can be flexibly assigned to interrupt servicing of a higher-priority event takes precedence over ser- channels. vicing of a lower-priority event. The processor provides support for five different types of events: Every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enable half-port assignment and • Emulation – An emulation event causes the processor to interrupt management. This includes masking, identification, enter emulation mode, allowing command and control of and clearing of requests. These registers also enable access to the the processor via the JTAG interface. respective pin states and use of the interrupt latches, regardless • Reset – This event resets the processor. of whether the interrupt is masked or not. Most control registers • Nonmaskable Interrupt (NMI) – The NMI event can be feature multiple MMR address entries to write-one-to-set or generated either by the software watchdog timer, by the write-one-to-clear them individually. NMI input signal to the processor, or by software. The
General-Purpose I/O (GPIO)
NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • Exceptions – Events that occur synchronously to program flow (in other words, the exception is taken before the • GPIO direction control register – Specifies the direction of instruction is allowed to complete). Conditions such as each individual GPIO pin as input or output. data alignment violations and undefined instructions cause • GPIO control and status registers – A “write one to mod- exceptions. ify” mechanism allows any combination of individual • Interrupts – Events that occur asynchronously to program GPIO pins to be modified in a single instruction, without flow. They are caused by input signals, timers, and other affecting the level of any other GPIO pins. peripherals, as well as by an explicit software instruction. • GPIO interrupt mask registers – Allow each individual
Core Event Controller (CEC)
GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate The CEC supports nine general-purpose interrupts (IVG15–7), hardware interrupts, while output pins can be triggered by in addition to the dedicated interrupt and exception events. Of software interrupts. these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for • GPIO interrupt sensitivity registers – Specify whether indi- software interrupt handlers. For more information, see the vidual pins are level- or edge-sensitive and specify—if ADSP-BF60x Processor Programmer’s Reference. edge-sensitive—whether just the rising edge or both the ris- ing and falling edges of the signal are significant.
System Event Controller (SEC) Pin Multiplexing
The SEC manages the enabling, prioritization, and routing of events from each system interrupt or fault source. Additionally, The processor supports a flexible multiplexing scheme that mul- it provides notification and identification of the highest priority tiplexes the GPIO pins with various peripherals. A maximum of active system interrupt request to each core and routes system 4 peripherals plus GPIO functionality is shared by each GPIO fault sources to its integrated fault management unit. pin. All GPIO pins have a bypass path feature – that is, when the output enable and the input enable of a GPIO pin are both
Trigger Routing Unit (TRU)
active, the data signal before the pad driver is looped back to the The TRU provides system-level sequence control without core receive path for the same GPIO pin. For more information, see intervention. The TRU maps trigger masters (generators of trig- GP I/O Multiplexing for 349-Ball CSP_BGA on Page 33. gers) to trigger slaves (receivers of triggers). Slave endpoints can
MEMORY ARCHITECTURE
be configured to respond to triggers in various ways. Common applications enabled by the TRU include: The processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal • Automatically triggering the start of a DMA sequence after memory, external memory, and I/O control registers, occupy a sequence from another DMA channel completes separate sections of this common address space. The memory • Software triggering portions of this address space are arranged in a hierarchical • Synchronization of concurrent activities structure to provide a good cost/performance balance of some very fast, low-latency core-accessible memory as cache or
Pin Interrupts
SRAM, and larger, lower-cost and performance interface-acces- Every port pin on the processor can request interrupts in either sible memory systems. See Figure 3 and Figure 4. an edge-sensitive or a level-sensitive manner with programma- ble polarity. Interrupt functionality is decoupled from GPIO Rev. A | Page 6 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide