Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 10

link to page 10 ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
USB Mode
12 MHz, or to support 24 MHz if the CLKDIV2 control register In USB mode, the codec supports digital audio sampling rates bit is activated. The programmer must set the appropriate sam- from 8 kHz to 96 kHz. USB mode is enabled on the codec pling rate in the SR control bits (Register R8, Bit D2 to Bit D5). to support the common universal serial bus (USB) clock rate of See Table 2 for sampling rates in USB mode.
Table 2. Sampling Rate Lookup Table, USB Mode (USB Enabled) CODEC_MCLK CODEC_MCLK ADC Sampling Rate DAC Sampling Rate USB SR [3:0] BOSR CODEC_BCLK (CLKDIV2 = 0) (CLKDIV2 = 1) (ADCLRC) (DACLRC) (MS = 1)1
12.000 MHz 24.000 MHz 8 kHz (CODEC_MCLK/1500) 8 kHz (CODEC_MCLK/1500) 1 0011 0 CODEC_MCLK 8 kHz (CODEC_MCLK/1500) 48 kHz (CODEC_MCLK/250) 1 0010 0 CODEC_MCLK 8.0214 kHz (CODEC_MCLK/1496) 8.0214 kHz (CODEC_MCLK/1496) 1 1011 1 CODEC_MCLK 8.0214 kHz (CODEC_MCLK/1496) 44.118 kHz (CODEC_MCLK/272) 1 1010 1 CODEC_MCLK 11.0259 kHz (CODEC_MCLK/1088) 11.0259 kHz (CODEC_MCLK/1088) 1 1100 1 CODEC_MCLK 12 kHz (CODEC_MCLK/1000) 12 kHz (CODEC_MCLK/1000) 1 1000 0 CODEC_MCLK 16 kHz (CODEC_MCLK/750) 16 kHz (CODEC_MCLK/750) 1 1010 0 CODEC_MCLK 22.0588 kHz (CODEC_MCLK/544) 22.0588 kHz (CODEC_MCLK/544) 1 1101 1 CODEC_MCLK 24 kHz (CODEC_MCLK/500) 24 kHz (CODEC_MCLK/500) 1 1110 0 CODEC_MCLK 32 kHz (CODEC_MCLK/375) 32 kHz (CODEC_MCLK/375) 1 0110 0 CODEC_MCLK 44.118 kHz (CODEC_MCLK/272) 8.0214 kHz (CODEC_MCLK/1496) 1 1001 1 CODEC_MCLK 44.118 kHz (CODEC_MCLK/272) 44.118 kHz (CODEC_MCLK/272) 1 1000 1 CODEC_MCLK 48 kHz (CODEC_MCLK/250) 8 kHz (CODEC_MCLK/1500) 1 0001 0 CODEC_MCLK 48 kHz (CODEC_MCLK/250) 48 kHz (CODEC_MCLK/250) 1 0000 0 CODEC_MCLK 88.235 kHz (CODEC_MCLK/136) 88.235 kHz (CODEC_MCLK/136) 1 1111 1 CODEC_MCLK 96 kHz (CODEC_MCLK/125) 96 kHz (CODEC_MCLK/125) 1 0111 0 CODEC_MCLK 1 CODEC_BCLK frequency is for master mode and slave right-justified mode only. Rev. A | Page 10 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide