Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 3

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 GENERAL DESCRIPTION
The ADSP-BF52x processors are members of the Blackfin fam- By integrating a rich set of industry-leading system peripherals ily of products, incorporating the Analog Devices/Intel Micro and memory, Blackfin processors are the platform of choice for Signal Architecture (MSA). Blackfin® processors combine a next-generation applications that require RISC-like program- dual-MAC state-of-the-art signal processing engine, the advan- mability, multimedia support, and leading-edge signal tages of a clean, orthogonal RISC-like microprocessor processing in one integrated package. instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set
PORTABLE LOW POWER ARCHITECTURE
architecture. Blackfin processors provide world-class power management The ADSP-BF52x processors are completely code compatible and performance. They are produced with a low power and low with other Blackfin processors. The ADSP-BF523/ voltage design methodology and feature on-chip dynamic ADSP-BF525/ADSP-BF527 processors offer performance up to power management, which is the ability to vary both the voltage 600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 pro- and frequency of operation to significantly lower overall power cessors offer performance up to 400 MHz and reduced static consumption. This capability can result in a substantial reduc- power consumption. Differences with respect to peripheral tion in power consumption, compared with just varying the combinations are shown in Table 1. frequency of operation. This allows longer battery life for portable appliances.
Table 1. Processor Comparison SYSTEM INTEGRATION
The ADSP-BF52x processors are highly integrated system-on-a- chip solutions for the next generation of embedded network
-BF522 -BF524 -BF526 -BF523 -BF525 -BF527
connected applications. By combining industry-standard inter- faces with a high performance signal processing core, cost-
Feature ADSP ADSP ADSP ADSP ADSP ADSP
effective applications can be developed quickly, without the H ost DMA 1 1 1 1 1 1 need for costly external components. The system peripherals USB – 1 1 – 1 1 include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB Ethernet MAC – – 1 – – 1 2.0 high speed OTG controller, a TWI controller, a NAND flash Internal Voltage Regulator – – – 1 1 1 controller, two UART ports, an SPI port, two serial ports (SPORTs), eight general purpose 32-bit timers with PWM capa- TWI 1 1 1 1 1 1 bility, a core timer, a real-time clock, a watchdog timer, a Host SPORTs 2 2 2 2 2 2 DMA (HOSTDP) interface, and a parallel peripheral interface UARTs 2 2 2 2 2 2 (PPI). SPI 1 1 1 1 1 1 GP Timers 8 8 8 8 8 8
PROCESSOR PERIPHERALS
GP Counter 1 1 1 1 1 1 The ADSP-BF52x processors contain a rich set of peripherals Watchd og Timers 1 1 1 1 1 1 connected to the core via several high bandwidth buses, provid- RTC 1 1 1 1 1 1 ing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). Para llel Periphe ral Interface 1 1 1 1 1 1 GPIOs 48 48 48 48 48 48 These Blackfin processors contain dedicated network commu- nication modules and high speed serial and parallel ports, an ) L1 Instruction SRAM 48K 48K 48K 48K 48K 48K interrupt controller for flexible management of interrupts from tes y L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K the on-chip peripherals or external sources, and power manage- (b L1 Data SRAM 32K 32K 32K 32K 32K 32K y ment control functions to tailor the performance and power L1 Data SRAM/Cache 32K 32K 32K 32K 32K 32K characteristics of the processor and system to many application L1 Scratchpad 4K 4K 4K 4K 4K 4K scenarios. Memor L3 Boot ROM 32K 32K 32K 32K 32K 32K All of the peripherals, except for the general-purpose I/O, TWI, Maximum Instruction Rate1 400 MHz 600 MHz real-time clock, and timers, are supported by a flexible DMA Maximum System Clock Speed 100 MHz 133 MHz structure. There are also separate memory DMA channels dedi- Package Options 289-Ball CSP_BGA cated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. 208-Ball CSP_BGA Multiple on-chip buses running at up to 133 MHz provide 1 Maximum instruction rate is not available with every possible SCLK selection. enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors include an on-chip voltage regulator in support of the proces- sor’s dynamic power management capability. The voltage Rev. D | Page 3 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide