Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 10

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
components as shown in Figure 4. unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.
RTXI RTXO R1
If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the
X1
hardware reset by interrogating a status bit in the watchdog timer control register.
C1 C2
The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK.
TIMERS SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
There are nine general-purpose programmable timer units in
C1 = 22 pF
the processors. Eight timers have an external pin that can be
C2 = 22 pF R1 = 10 M
: configured either as a pulse width modulator (PWM) or timer
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
output, as an input to clock the timer, or as a mechanism for
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
measuring pulse widths and periods of external events. These
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
timers can be synchronized to an external clock input to the sev- Figure 4. External Components for RTC eral other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. The RTC peripheral has dedicated power supply pins so that it The timer units can be used in conjunction with the two UARTs can remain powered up and clocked even when the rest of the to measure the width of the pulses in the data stream to provide processor is in a low power state. The RTC provides several pro- a software auto-baud detect function for the respective serial grammable interrupt options, including interrupt per second, channels. minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm The timers can generate interrupts to the processor core provid- time. ing periodic events for synchronization, either to the system clock or to a count of external signals. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists In addition to the eight general-purpose programmable timers, of four counters: a 60-second counter, a 60-minute counter, a a ninth timer is also provided. This extra timer is clocked by the 24-hour counter, and an 32,768-day counter. internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the
UP/DOWN COUNTER AND THUMBWHEEL
alarm control register. There are two alarms: The first alarm is
INTERFACE
for a time of day. The second alarm is for a day and time of that day. A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial The stopwatch function counts down from a programmed drives or manual thumb wheels. The counter can also operate in value, with one-second resolution. When the stopwatch is general-purpose up/down count modes. Then, count direction enabled and the counter underflows, an interrupt is generated. is either controlled by a level-sensitive input pin or by two edge Like the other peripherals, the RTC can wake up the processor detectors. from sleep mode upon generation of any RTC wake-up event. A third input can provide flexible zero marker support and can Additionally, an RTC wakeup event can wake up the processor alternatively be used to input the push-button signal of thumb from deep sleep mode or cause a transition from the hibernate wheels. All three pins have a programmable debouncing circuit. state. An internal signal forwarded to the timer unit enables one timer
WATCHDOG TIMER
to measure the intervals between count events. Boundary regis- ters enable auto-zero operation or simple system warning by The processor includes a 32-bit timer that can be used to imple- interrupts when programmable count values are exceeded. ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known
SERIAL PORTS
state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer The processors incorporate two dual-channel synchronous expires before being reset by software. The programmer initial- serial ports (SPORT0 and SPORT1) for serial and multiproces- izes the count value of the timer, enables the appropriate sor communications. The SPORTs support the following interrupt, then enables the timer. Thereafter, the software must features: reload the counter before it counts to zero from the pro- • I2S capable operation. grammed value. This protects the system from remaining in an Rev. D | Page 10 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide