Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 9

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
unmasked and is processed by the system when asserted. A Examples of DMA types supported by the processor DMA con- cleared bit in the register masks the peripheral event, pre- troller include: venting the processor from servicing the event. • A single, linear buffer that stops upon completion. • SIC interrupt status registers (SIC_ISRx) — As multiple • A circular, auto-refreshing buffer that interrupts on each peripherals can be mapped to a single event, these registers full or fractionally full buffer. allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the • 1-D or 2-D DMA using a linked list of descriptors. peripheral is asserting the interrupt, and a cleared bit indi- • 2-D DMA using an array of descriptors, specifying only the cates the peripheral is not asserting the event. base DMA address within a common page. • SIC interrupt wakeup enable registers (SIC_IWRx) — By In addition to the dedicated peripheral DMA channels, there are enabling the corresponding bit in these registers, a periph- two memory DMA channels provided for transfers between the eral can be configured to wake up the processor, should the various memories of the processor system. This enables trans- core be idled or in sleep mode when the event is generated. fers of blocks of data between any of the memories—including For more information see Dynamic Power Management on external SDRAM, ROM, SRAM, and flash memory—with mini- Page 14. mal processor intervention. Memory DMA transfers can be Because multiple interrupt sources can map to a single general- controlled by a very flexible descriptor-based methodology or purpose interrupt, multiple pulse assertions can occur simulta- by a standard register-based autobuffer mechanism. neously, before or during interrupt processing for an interrupt The processor also has an external DMA controller capability event already detected on this interrupt input. The IPEND via dual external DMA request pins when used in conjunction register contents are monitored by the SIC as the interrupt with the external bus interface unit (EBIU). This functionality acknowledgement. can be used when a high speed interface is required for external The appropriate ILAT register bit is set when an interrupt rising FIFOs and high bandwidth communications peripherals such as edge is detected (detection requires two core clock cycles). The USB 2.0. It allows control of the number of data transfers for bit is cleared when the respective IPEND register bit is set. The memory DMA. The number of transfers per edge is program- IPEND bit indicates that the event has entered into the proces- mable. This feature can be programmed to allow memory sor pipeline. At this point the CEC recognizes and queues the DMA to have an increased priority on the external bus relative next rising edge event on the corresponding event input. The to the core. minimum latency from the rising edge transition of the general-
HOST DMA PORT
purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- The host port interface allows an external host to be a DMA ing on the activity within and the state of the processor. master to transfer data in and out of the device. The host device masters the transactions and the Blackfin processor is the
DMA CONTROLLERS
DMA slave. The processor has multiple, independent DMA channels that The host port is enabled through the PAB interface. Once support automated data transfers with minimal overhead for enabled, the DMA is controlled by the external host, which can the processor core. DMA transfers can occur between the then program the DMA to send/receive data to any valid inter- processor's internal memories and any of its DMA-capable nal or external memory location. peripherals. Additionally, DMA transfers can be accomplished The host port interface controller has the following features. between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including • Allows external master to configure DMA read/write data the SDRAM controller and the asynchronous memory control- transfers and read port status. ler. DMA-capable peripherals include the Ethernet MAC, NFC, • Uses asynchronous memory protocol for external interface. HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi- • 8-/16-bit external data interface to host device. vidual DMA-capable peripheral has at least one dedicated DMA channel. • Half duplex operation. The processor DMA controller supports both one-dimensional • Little-/big-endian data transfer. (1-D) and two-dimensional (2-D) DMA transfers. DMA trans- • Acknowledge mode allows flow control on host fer initialization can be implemented from registers or from sets transactions. of parameters called descriptor blocks. • Interrupt mode guarantees a burst of FIFO depth host The 2-D DMA capability supports arbitrary row and column transactions. sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the
REAL-TIME CLOCK
column step size can be less than the row step size, allowing The real-time clock (RTC) provides a robust set of digital watch implementation of interleaved data streams. This feature is features, including current time, stopwatch, and alarm. The especially useful in video applications where data can be de- RTC is clocked by a 32.768 kHz crystal external to the Blackfin interleaved on the fly. processor. Connect RTC pins RTXI and RTXO with external Rev. D | Page 9 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide