Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Blackfin Embedded Processor |
| Pages / Page | 102 / 2 — ADSP-BF542/. ADSP-BF544. /ADSP-BF547/. ADSP-BF548/. ADSP-BF549. TABLE OF … |
| Revision | E |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
ADSP-BF542/. ADSP-BF544. /ADSP-BF547/. ADSP-BF548/. ADSP-BF549. TABLE OF CONTENTS. REVISION HISTORY. 03/14—Rev. D to Rev. E
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ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549 TABLE OF CONTENTS
Features ... 1 Voltage Regulation .. 16 Memory .. 1 Clock Signals .. 17 Peripherals ... 1 Booting Modes ... 18 General Description ... 3 Instruction Set Description .. 21 Low Power Architecture ... 4 Development Tools .. 21 System Integration .. 4 MXVR Board Layout Guidelines ... 22 Blackfin Processor Peripherals ... 4 Additional information ... 23 Blackfin Processor Core .. 4 Related Signal Chains ... 23 Memory Architecture .. 6 Lockbox Secure Technology Disclaimer .. 23 DMA Controllers .. 9 Pin Descriptions .. 24 Real-Time Clock ... 10 Specifications .. 34 Watchdog Timer .. 10 Operating Conditions ... 34 Timers ... 10 Electrical Characteristics ... 36 Up/Down Counter and Thumbwheel Interface .. 11 Absolute Maximum Ratings ... 40 Serial Ports (SPORTs) .. 11 ESD Sensitivity ... 41 Serial Peripheral Interface (SPI) Ports .. 11 Package Information .. 41 UART Ports (UARTs) .. 11 Timing Specifications ... 42 Controller Area Network (CAN) .. 12 Output Drive Currents ... 88 TWI Controller Interface .. 12 Test Conditions .. 90 Ports .. 12 Capacitive Loading .. 90 Pixel Compositor (PIXC) .. 13 Typical Rise and Fall Times ... 91 Enhanced Parallel Peripheral Interface (EPPI) ... 13 Thermal Characteristics .. 93 USB On-the-Go Dual-Role Device Controller .. 13 400-Ball CSP_BGA Package .. 94 ATA/ATAPI-6 Interface ... 14 Outline Dimensions .. 100 Keypad Interface ... 14 Surface-Mount Design .. 100 Secure Digital (SD)/SDIO Controller ... 14 Automotive Products .. 101 Code Security .. 14 Ordering Guide ... 101 Media Transceiver MAC Layer (MXVR) .. 14 Dynamic Power Management .. 15
REVISION HISTORY 03/14—Rev. D to Rev. E
Added/changed package dimensions to Figure 88 in Updated Development Tools .. 21 Outline Dimensions .. 100 Corrected SPI2 pin count in Port B configuration in Added low Alpha Package model to Ordering Guide ... 101 Pin Multiplexing .. 24 Corrected typographical error of parameter name in External DMA Request Timing ... 58 Added note to Table 42 in Serial Ports—Enable and Three-State .. 63 Corrected tWL and tWH minimum specifications from tSCLK +1 to 1 × tSCLK in Timer Cycle Timing ... 69 Rev. E | Page 2 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-BF542/ ADSP-BF544 /ADSP-BF547/ ADSP-BF548/ ADSP-BF549 TABLE OF CONTENTS
Features ... 1 Voltage Regulation .. 16 Memory .. 1 Clock Signals .. 17 Peripherals ... 1 Booting Modes ... 18 General Description ... 3 Instruction Set Description .. 21 Low Power Architecture ... 4 Development Tools .. 21 System Integration .. 4 MXVR Board Layout Guidelines ... 22 Blackfin Processor Peripherals ... 4 Additional information ... 23 Blackfin Processor Core .. 4 Related Signal Chains ... 23 Memory Architecture .. 6 Lockbox Secure Technology Disclaimer .. 23 DMA Controllers .. 9 Pin Descriptions .. 24 Real-Time Clock ... 10 Specifications .. 34 Watchdog Timer .. 10 Operating Conditions ... 34 Timers ... 10 Electrical Characteristics ... 36 Up/Down Counter and Thumbwheel Interface .. 11 Absolute Maximum Ratings ... 40 Serial Ports (SPORTs) .. 11 ESD Sensitivity ... 41 Serial Peripheral Interface (SPI) Ports .. 11 Package Information .. 41 UART Ports (UARTs) .. 11 Timing Specifications ... 42 Controller Area Network (CAN) .. 12 Output Drive Currents ... 88 TWI Controller Interface .. 12 Test Conditions .. 90 Ports .. 12 Capacitive Loading .. 90 Pixel Compositor (PIXC) .. 13 Typical Rise and Fall Times ... 91 Enhanced Parallel Peripheral Interface (EPPI) ... 13 Thermal Characteristics .. 93 USB On-the-Go Dual-Role Device Controller .. 13 400-Ball CSP_BGA Package .. 94 ATA/ATAPI-6 Interface ... 14 Outline Dimensions .. 100 Keypad Interface ... 14 Surface-Mount Design .. 100 Secure Digital (SD)/SDIO Controller ... 14 Automotive Products .. 101 Code Security .. 14 Ordering Guide ... 101 Media Transceiver MAC Layer (MXVR) .. 14 Dynamic Power Management .. 15
REVISION HISTORY 03/14—Rev. D to Rev. E
Added/changed package dimensions to Figure 88 in Updated Development Tools .. 21 Outline Dimensions .. 100 Corrected SPI2 pin count in Port B configuration in Added low Alpha Package model to Ordering Guide ... 101 Pin Multiplexing .. 24 Corrected typographical error of parameter name in External DMA Request Timing ... 58 Added note to Table 42 in Serial Ports—Enable and Three-State .. 63 Corrected tWL and tWH minimum specifications from tSCLK +1 to 1 × tSCLK in Timer Cycle Timing ... 69 Rev. E | Page 2 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
