Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 9

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ADSP-BF542 /ADSP-BF544 /ADSP-BF547/ ADSP-BF548 /ADSP-BF549
• SIC interrupt mask registers (SIC_IMASKx). These regis- DAB16 bus. Individual DMA channels have fixed access prior- ters control the masking and unmasking of each peripheral ity on the DAB buses. DMA priority of peripherals is managed interrupt event. When a bit is set in a register, that periph- by a flexible peripheral-to-DMA channel assignment scheme. eral event is unmasked and is processed by the system All four DMA controllers use the same 32-bit DCB bus to when asserted. A cleared bit in the register masks the exchange data with L1 memory. This includes L1 ROM, but peripheral event, preventing the processor from servicing excludes scratchpad memory. Fine granulation of L1 memory the event. and special DMA buffers minimize potential memory conflicts • SIC interrupt status registers (SIC_ISRx). As multiple when the L1 memory is accessed simultaneously by the core. peripherals can be mapped to a single event, these registers Similarly, there are dedicated DMA buses between the external allow the software to determine which peripheral event bus interface unit (EBIU) and the three DMA controllers source triggered the interrupt. A set bit indicates the (DMAC1, DMAC0, and USB) that arbitrate DMA accesses to peripheral is asserting the interrupt, and a cleared bit indi- external memories and the boot ROM. cates the peripheral is not asserting the event. The ADSP-BF54x Blackfin processors’ DMA controllers sup- • SIC interrupt wakeup enable registers (SIC_IWRx). By port both 1-dimensional (1D) and 2-dimensional (2D) DMA enabling the corresponding bit in this register, a peripheral transfers. DMA transfer initialization can be implemented from can be configured to wake up the processor, should the registers or from sets of parameters called descriptor blocks. core be idled or in Sleep mode when the event is generated. The 2D DMA capability supports arbitrary row and column (For more information, see Dynamic Power Management sizes up to 64K elements by 64K elements, and arbitrary row on Page 15.) and column step sizes up to ±32K elements. Furthermore, the Because multiple interrupt sources can map to a single general- column step size can be less than the row step size, allowing purpose interrupt, multiple pulse assertions can occur simulta- implementation of interleaved data streams. This feature is neously, before or during interrupt processing for an interrupt especially useful in video applications where data can be de- event already detected on this interrupt input. The IPEND reg- interleaved on the fly. ister contents are monitored by the SIC as the interrupt Examples of DMA types supported by the ADSP-BF54x Black- acknowledgement. fin processors’ DMA controllers include: The appropriate ILAT register bit is set when an interrupt rising • A single, linear buffer that stops upon completion edge is detected. (Detection requires two core clock cycles.) The bit is cleared when the respective IPEND register bit is set. The • A circular, auto-refreshing buffer that interrupts on each IPEND bit indicates that the event has entered into the proces- full or fractionally full buffer sor pipeline. At this point the CEC recognizes and queues the • 1D or 2D DMA using a linked list of descriptors next rising edge event on the corresponding event input. The • 2D DMA using an array of descriptors, specifying only the minimum latency from the rising edge transition of the general- base DMA address within a common page purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- In addition to the dedicated peripheral DMA channels, the ing on the activity within and the state of the processor. DMAC1 and DMAC0 controllers each feature two memory DMA channel pairs for transfers between the various memories
DMA CONTROLLERS
of the ADSP-BF54x Blackfin processors. This enables transfers ADSP-BF54x Blackfin processors have multiple, independent of blocks of data between any of the memories—including DMA channels that support automated data transfers with min- external DDR, ROM, SRAM, and flash memory—with minimal imal overhead for the processor core. DMA transfers can occur processor intervention. Like peripheral DMAs, memory DMA between the ADSP-BF54x processors’ internal memories and transfers can be controlled by a very flexible descriptor-based any of the DMA-capable peripherals. Additionally, DMA trans- methodology or by a standard register-based autobuffer fers can be accomplished between any of the DMA-capable mechanism. peripherals and external devices connected to the external The memory DMA channels of the DMAC1 controller memory interfaces, including DDR and asynchronous memory (MDMA2 and MDMA3) can be controlled optionally by the controllers. external DMA request input pins. When used in conjunction While the USB controller and MXVR have their own dedicated with the External Bus Interface Unit (EBIU), this handshaked DMA controllers, the other on-chip peripherals are managed by memory DMA (HMDMA) scheme can be used to efficiently two centralized DMA controllers, called DMAC1 (32-bit) and exchange data with block-buffered or FIFO-style devices con- DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA nected externally. Users can select whether the DMA request controller manages 12 independent peripheral DMA channels, pins control the source or the destination side of the memory as well as two independent memory DMA streams. The DMA. It allows control of the number of data transfers for DMAC1 controller masters high-bandwidth peripherals over a memory DMA. The number of transfers per edge is program- dedicated 32-bit DMA access bus (DAB32). Similarly, the mable. This feature can be programmed to allow memory DMA DMAC0 controller masters most serial interfaces over the 16-bit to have an increased priority on the external bus relative to the core. Rev. E | Page 9 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide