Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 10

ADSP-BF534/ADSP-BF536/ADSP-BF537 SERIAL PORTS (SPORTs)
port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors environments. incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor commu- The SPI port’s baud rate and clock phase/polarities are pro- nications. The SPORTs support the following features: grammable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The • I2S capable operation. SPI’s DMA controller can only service unidirectional accesses at • Bidirectional operation – Each SPORT has two sets of inde- any given time. pendent transmit and receive pins, enabling eight channels The SPI port’s clock rate is calculated as: of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port f SPI Clock Rate SCLK = ------------------ has a data register for transferring data words to and from 2  SPI_BAUD other processor components and shift registers for shifting data in and out of the data registers. where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies During transfers, the SPI port simultaneously transmits and ranging from (f receives by serially shifting data in and out on its two serial data SCLK/131,070) Hz to (fSCLK/2) Hz. lines. The serial clock line synchronizes the shifting and sam- • Word length – Each SPORT supports serial data words pling of data on the two serial data lines. from 3 bits to 32 bits in length, transferred most significant bit first or least significant bit first.
UART PORTS
• Framing – Each transmit and receive port can run with or The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro- without frame sync signals for each data word. Frame sync vide two full-duplex universal asynchronous receiver and signals can be generated internally or externally, active high transmitter (UART) ports, which are fully compatible with PC- or low, and with either of two pulse widths and early or late standard UARTs. Each UART port provides a simplified UART frame sync. interface to other peripherals or hosts, supporting full-duplex, • Companding in hardware – Each SPORT can perform DMA-supported, asynchronous transfers of serial data. A A-law or μ-law companding according to ITU recommen- UART port includes support for five to eight data bits, one or dation G.711. Companding can be selected on the transmit two stop bits, and none, even, or odd parity. Each UART port and/or receive channel of the SPORT without additional supports two modes of operation: latencies. • PIO (programmed I/O) – The processor sends or receives • DMA operations with single-cycle overhead – Each SPORT data by writing or reading I/O mapped UART registers. can automatically receive and transmit multiple buffers of The data is double-buffered on both transmit and receive. memory data. The processor can link or chain sequences of • DMA (direct memory access) – The DMA controller trans- DMA transfers between a SPORT and memory. fers both transmit and receive data. This reduces the • Interrupts – Each transmit and receive port generates an number and frequency of interrupts required to transfer interrupt upon completing the transfer of a data word or data to and from memory. The UART has two dedicated after transferring an entire data buffer, or buffers, DMA channels, one for transmit and one for receive. These through DMA. DMA channels have lower default priority than most DMA channels because of their relatively low service rates. • Multichannel capability – Each SPORT supports 128 chan- nels out of a 1024-channel window and is compatible with Each UART port’s baud rate, serial data format, error code gen- the H.100, H.110, MVIP-90, and HMVIP standards. eration and status, and interrupts are programmable:
SERIAL PERIPHERAL INTERFACE (SPI) PORT
• Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK/16) bits per second. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have • Supporting data formats from 7 bits to 12 bits per frame. an SPI-compatible port that enables the processor to communi- cate with multiple SPI-compatible devices. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master Input- The UART port’s clock rate is calculated as: Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI f chip select input pin (SPISS) lets other SPI devices select the UART Clock Rate SCLK = ------------------------- processor, and seven SPI chip select output pins (SPISEL7–1) let 16  UARTx_Divisor the processor select other SPI devices. The SPI select pins are where the 16-bit UARTx_Divisor comes from the UARTx_DLH reconfigured programmable flag pins. Using these pins, the SPI register (most significant 8 bits) and UARTx_DLL register (least significant 8 bits). Rev. J | Page 10 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide