Datasheet AD5231 (Analog Devices) - 8

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AD5231 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS O1 1 16 O2 CLK 2 15 RDY SDI 3 14 CS SDO 4 AD5231 13 PR TOP VIEW GND 5 12 (Not to Scale) WP VSS 6 11 VDD T 7 10 A
005
B 8 9 W
02739- Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 O1 Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit format is 0x310001. 2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. 3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 5 GND Ground Pin. Logic ground reference. 6 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual-supply applications, it must be able to sink 40 mA for 25 ms when storing data to EEMEM. 7 T Reserved for factory testing. Connect to VDD or VSS. 8 B Terminal B of RDAC. 9 W Wiper Terminal of RDAC. ADDR (RDAC) = 0x0. 10 A Terminal A of RDAC. 11 VDD Positive Power Supply Pin. 12 WP Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Tie WP to VDD, if not used. 13 PR Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated at the logic high transition. Tie PR to VDD, if not used. 14 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. 15 RDY Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR. 16 O2 Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit format is 0x310002. Rev. D | Page 8 of 28 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions Timing Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Scratchpad and EEMEM Programming Basic Operation EEMEM Protection Digital Input/Output Configuration Serial Data Interface Daisy-Chain Operation Terminal Voltage Operation Range Power-Up Sequence Latched Digital Outputs Advanced Control Modes Linear Increment and Decrement Instructions Logarithmic Taper Mode Adjustment Using Additional Internal Nonvolatile EEMEM RDAC Structure Programming the Variable Resistor Rheostat Operation Programming the Potentiometer Divider Voltage Output Operation Programming Examples Flash/EEMEM Reliability Applications Bipolar Operation from Dual Supplies High Voltage Operation Bipolar Programmable Gain Amplifier 10-Bit Bipolar DAC 10-Bit Unipolar DAC Programmable Voltage Source with Boosted Output Programmable Current Source Programmable Bidirectional Current Source Resistance Scaling RDAC Circuit Simulation Model Outline Dimensions Ordering Guide