Datasheet ADSP-SC582, ADSP-SC583, ADSP-SC584, ADSP-SC587, ADSP-SC589, ADSP-21583, ADSP-21584, ADSP-21587 (Analog Devices) - 10

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ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 Single-Cycle Fetch of Instructional Four Operands SYSTEM INFRASTRUCTURE
The ADSP-SC58x/ADSP-2158x processors feature an enhanced The following sections describe the system infrastructure of the Harvard architecture in which the DM bus transfers data and ADSP-SC58x/ADSP-2158x processors. PM bus transfers both instructions and data.
System L2 Memory
With the separate program memory bus, data memory buses, and on-chip instruction conflict-cache, the processor can simul- A system L2 SRAM memory of 2 Mb (256 kB) and two ROM taneously fetch four operands (two over each data bus) and one memories, each 2 Mb (256 kB), are available to both SHARC+ instruction from the conflict cache, in a single cycle. cores, the Arm Cortex-A5 core, and the system DMA channels (see Table 5). All L2 SRAM/ROM blocks are subdivided into
Core Event Controller (CEC)
eight banks to support concurrent access to the L2 memory The SHARC+ core generates various core interrupts (including ports. Memory accesses to the L2 memory space are multicycle arithmetic and circular buffer instruction flow exceptions) and accesses by both the Arm Cortex-A5 and SHARC+ cores. SEC events (debug/monitor and software). The core only The memory space is used for various cases including responds to unmasked interrupts (enabled in the IMASK • Arm Cortex-A5 to SHARC+ core data sharing and inter- register). core communications
Instruction Conflict-Cache
• Accelerator and peripheral sources and destination mem- The processors include a 32-entry instruction cache that enables ory to avoid accessing data in the external memory three-bus operation for fetching an instruction and four data • A location for DMA descriptors values. The cache is selective—only the instructions that require • Storage for additional data for either the Arm Cortex-A5 or fetches conflict with the PM bus data accesses cache. This cache SHARC+ cores to avoid external memory latencies and allows full speed execution of core, looped operations, such as reduce external memory bandwidth digital filter multiply accumulates, and fast Fourier transforms (FFT) butterfly processing. The conflict cache serves for on-chip • Storage for incoming Ethernet traffic to improve bus conflicts only. performance • Storage for data coefficient tables cached by the
Branch Target Buffer/Branch Predictor
SHARC+ core Implementation of a hardware-based branch predictor (BP) and See the System Memory Protection Unit (SMPU) section for branch target buffer (BTB) reduce branch delay. The program options in limiting access by specific cores and DMA masters. sequencer supports efficient branching using the BTB for condi- tional and unconditional instructions. The Arm Cortex-A5 core has an L1 instruction and data cache, each of which is 32 kB in size. The core also has an L2 cache
Addressing Spaces
controller of 256 kB. When enabling the caches, accesses to all In addition to traditionally supported long word, normal word, other memory spaces (internal and external) go through the extended precision word and short word addressing aliases, the cache. processors support byte addressing for the data and instruction
SHARC+ Core L1 Memory in Multiprocessor Space
accesses. The enhanced ISA/VISA provides new instructions for accessing all sizes of data from byte space as well as converting The Arm Cortex-A5 core can access the L1 memory of the word addresses to byte and byte to word addresses. SHARC+ core. See Table 6 for the L1 memory address in multi- processor space. The SHARC+ core can access the L1 memory
Additional Features
of the other SHARC+ core in the multiprocessor space. The enhanced ISA/VISA of the ADSP-SC58x/ADSP-2158x pro-
One Time Programmable Memory (OTP)
cessors also provides a memory barrier instruction for data synchronization, exclusive data access support for multicore The processors feature 7 kB of one time programmable (OTP) data sharing, and exclusive data access to enable multiprocessor memory which is memory-map accessible. This memory con- programming. To enhance the reliability of the application, L1 tains space for programmable unique keys and supports secure data RAMs support parity error detection logic for every byte. boot and secure operation. Additionally, the processors detect illegal opcodes. Core inter-
I/O Memory Space
rupts flag both errors. Master ports of the core also detect for failed external accesses. The static memory controller (SMC) is programmed to control up to two blocks of external memories or memory-mapped devices, with flexible timing parameters. Each block occupies an 8 Kb segment regardless of the size of the device used. Mapped I/Os also include PCIe data and SPI2 memory address space (see Table 7). Rev. B | Page 10 of 173 | December 2018 Document Outline System Features Memory Additional Features Table of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC58x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC58x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers (USTAT) Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict-Cache Branch Target Buffer/Branch Predictor Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant C ode (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Arm TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Ports (LP) ADC Control Module (ACM) Interface 3-Phase Pulse Width Modulator (PWM) Units Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) PCI Express (PCIe) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller Media Local Bus (Media LB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration FFT/IFFT Accelerator Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator Harmonic Analysis Engine (HAE) Sinus Cardinalis (SINC) Filter Digital Transmission Content Protection (DTCP) System Design Clock Management Reset Control Unit (RCU) Real-Time Clock (RTC) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 349-Ball CSP_BGA Package 529-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 529-Ball CSP_BGA Package ADSP-SC58x/ADSP-2158x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LP) Serial Ports (SPORT) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port SPI Port—Master Timing SPI Port—Slave Timing SPI Port—SPI Ready (SPIx_RDY) Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose I/O Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing PWM — Medium Precision (MP) Mode Timing PWM — Heightened Precision (HP) Mode Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) PCI Express (PCIe) 10/100 EMAC Timing (ETH0 and ETH1) 10/100/1000 EMAC Timing (ETH0 Only) Sinus Cardinalis (SINC) Filter Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode Media LB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 349-Ball CSP_BGA ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 529-Ball CSP_BGA Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide