Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 6

ADSP-21371/ ADSP-21375 Table 3. ADSP-21371 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)
BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved Reserved 0x0004 8000–0x0004 BFFF 0x0008 AAAA–0x0008 FFFF 0x0009 0000–0x0009 7FFF 0x0012 0000–0x0012 FFFF BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM 0x0004 C000–0x0004 CFFF 0x0009 0000–0x0009 1554 0x0009 8000–0x0009 9FFF 0x0013 0000–0x0013 3FFF Reserved Reserved Reserved Reserved 0x0004 D000–0x0004 FFFF 0x0009 1555–0x0009 FFFF 0x0009 A000–0x0009 FFFF 0x0013 4000–0x0013 FFFF BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000–0x0005 BFFF 0x000A AAAA–0x000A FFFF 0x000B 0000–0x000B 7FFF 0x0016 0000–0x0016 FFFF BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM 0x0005 C000–0x0005 CFFF 0x000B 0000–0x000B 1554 0x000B 8000–0x000B 9FFF 0x0017 0000–0x0017 3FFF Reserved Reserved Reserved Reserved 0x0005 D000–0x0005 FFFF 0x000B 1555–0x000B FFFF 0x000B A000–0x000B FFFF 0x0017 4000–0x0017 FFFF BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF Reserved Reserved Reserved Reserved 0x0006 1000–0x0006 FFFF 0x000C 1555–0x000D FFFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF Reserved Reserved Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF external code, executing exclusively from internal ROM. Addi-
External Port
tionally, the processor is not freely accessible via the JTAG port. The external port on the ADSP-21371/ADSP-21375 SHARC Instead, a unique 64-bit key, which must be scanned in through processors provide a high performance, glueless interface to a the JTAG or Test Access Port will be assigned to each customer. wide variety of industry-standard memory devices. The 32-bit The device will ignore a wrong key. Emulation features and wide bus (ADSP-21371) may be used to interface to synchro- external boot modes are only available after the correct key is nous and/or asynchronous memory devices through the use of scanned. its separate internal memory controllers: the first is an SDRAM
FAMILY PERIPHERAL ARCHITECTURE
controller for connection of industry-standard synchronous DRAM devices and DIMMs (dual inline memory module), The ADSP-21371/ADSP-21375 family contains a rich set of while the second is an asynchronous memory controller peripherals that support a wide variety of applications, includ- intended to interface to a variety of memory devices. Four ing high quality audio, medical imaging, communications, memory select pins enable up to four separate devices to coexist, military, test equipment, 3D graphics, speech recognition, mon- supporting any desired combination of synchronous and asyn- itor control, imaging, and other applications. chronous device types. Rev. D | Page 6 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide