Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 6

ADSP-21362/ADSP-21363/ADSP -21364/ADSP-21365/ADSP-21366 Table 3. ADSP-2136x Internal Memory Space IOP Registers 0x0000 0000–0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM Block 0 ROM Block 0 ROM Block 0 ROM 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved 0x0004 8000–0x0004 BFFF 0x0009 0000–0x0009 7FFF 0x0012 0000–0x0012 FFFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 C000–0x0004 FFFF 0x0009 0000–0x0009 5554 0x0009 8000–0x0009 FFFF 0x0013 0000–0x0013 FFFF Block 1 ROM Block 1 ROM Block 1 ROM Block 1 ROM 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved 0x0005 8000–0x0005 BFFF 0x000B 0000–0x000B 7FFF 0x0016 0000–0x0016 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 C000–0x0005 FFFF 0x000B 0000–0x000B 5554 0x000B 8000–0x000B FFFF 0x0017 0000–0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 1FFF 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF 0x0018 0000–0x0018 7FFF Reserved Reserved Reserved 0x0006 2000–0x0006 FFFF 0x000C 4000–0x000D FFFF 0x0018 8000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 1FFF 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF 0x001C 0000–0x001C 7FFF Reserved Reserved Reserved 0x0007 2000–0x0007 FFFF 0x000E 4000–0x000F FFFF 0x001C 8000–0x001F FFFF Reserved 0x0020 0000–0xFFFF FFFF or test access port, is assigned to each customer. The device
Serial Peripheral (Compatible) Interface
ignores a wrong key. Emulation features and external boot The processors contain two serial peripheral interface ports modes are only available after the correct key is scanned. (SPIs). The SPI is an industry-standard synchronous serial link,
FAMILY PERIPHERAL ARCHITECTURE
enabling the processor’s SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data The ADSP-2136x family contains a rich set of peripherals that pins, one device select pin, and one clock pin. It is a full-duplex support a wide variety of applications, including high quality synchronous serial interface, supporting both master and slave audio, medical imaging, communications, military, test equip- modes and can operate at a maximum baud rate of fPCLK/4. ment, 3D graphics, speech recognition, monitor control, imaging, and other applications. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either
Parallel Port
acting as a master or slave device. The ADSP-2136x SPI- compatible peripheral implementation also features program- The parallel port provides interfaces to SRAM and peripheral mable baud rate, clock phase, and polarities. The SPI- devices. The multiplexed address and data pins (AD15–0) can compatible port uses open drain drivers to support a multimas- access 8-bit devices with up to 24 bits of address, or 16-bit ter configuration and to avoid data contention. devices with up to 16 bits of address. In either mode, 8-bit or 16-bit, the maximum data transfer rate is fPCLK/4.
Pulse-Width Modulation
DMA transfers are used to move data to and from internal The entire PWM module has four groups of four PWM outputs memory. Access to the core is also facilitated through the paral- each. Therefore, this module generates 16 PWM outputs in lel port register read/write functions. The RD, WR, and ALE total. Each PWM group produces two pairs of PWM signals on (address latch enable) pins are the control pins for the the four PWM outputs. parallel port. The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can Rev. J | Page 6 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide