Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 8

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ADSP-21362/ADSP-21363/ADSP -21364/ADSP-21365/ADSP-21366
audio channels in I2S, left-justified sample pair, or right-justi-
SYSTEM DESIGN
fied mode. One frame sync cycle indicates one 64-bit left/right The following sections provide an introduction to system design pair, but data is sent to the FIFO as 32-bit words (that is, one- options and power supply issues. half of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
Program Booting
right-justified formats. The internal memory of the processor boots at system power-up
Precision Clock Generator (PCG)
from an 8-bit EPROM via the parallel port, an SPI master, an The precision clock generators (PCG) consist of two units, each SPI slave, or an internal boot. Booting is determined by the boot of which generates a pair of signals (clock and frame sync) configuration (BOOT_CFG1–0) pins in Table 5. Selection of the derived from a clock input signal. The units, A and B, are identi- boot source is controlled via the SPI as either a master or slave cal in functionality and operate independently of each other. device, or it can immediately begin executing from ROM. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.
Table 5. Boot Mode Selection Peripheral Timers BOOT_CFG1–0 Booting Mode
00 SPI Slave Boot The following three general-purpose timers can generate peri- odic interrupts and be independently set to operate in one of 01 SPI Master Boot three modes: 10 Parallel Port Boot via EPROM • Pulse waveform generation mode 11 No booting occurs. Processor executes from internal ROM after reset. • Pulse width count/capture mode • External event watchdog mode
Phase-Locked Loop
Each general-purpose timer has one bidirectional pin and four The processors use an on-chip phase-locked loop (PLL) to gen- registers that implement its mode of operation: a 6-bit configu- erate the internal clock for the core. On power-up, the ration register, a 32-bit count register, a 32-bit period register, CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and and a 32-bit pulse width register. A single control and status 6:1. After booting, numerous other ratios can be selected via register enables or disables all three general-purpose timers software control. independently. The ratios are made up of software configurable numerator val-
I/O PROCESSOR FEATURES
ues from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. The processor’s I/O provides many channels of DMA and con- trols the extensive set of peripherals described in the previous
Power Supplies
sections. The processor has a separate power supply connection for the
DMA Controller
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the The processor’s on-chip DMA controllers allow data transfers 1.2 V requirement for K, B, and Y grade models, and the 1.0 V without processor intervention. The DMA controller operates requirement for Y models. (For information on the temperature independently and invisibly to the processor core, allowing ranges offered for this product, see Operating Conditions on DMA operations to occur while the core is simultaneously exe- Page 14, Package Information on Page 16, and Ordering Guide cuting its program instructions. DMA transfers can occur on Page 56.) The external supply must meet the 3.3 V require- between the processor’s internal memory and its serial ports, the ment. All external supply pins must be connected to the same SPI-compatible (serial peripheral interface) ports, the IDP power supply. (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec-
Table 4. DMA Channels
ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the
Peripheral ADSP-2136x
AVDD/AVSS pins. For an example circuit, see Figure 3. (A SPORTs 12 recommended ferrite chip is the muRata BLM18AG102SN1D.) To reduce noise coupling, the PCB should use a parallel pair of IDP/PDAP 8 power and ground planes for VDDINT and GND. Use wide traces SPI 2 to connect the bypass capacitors to the analog power (AVDD) MTM/DTCP 2 and ground (AVSS) pins. Note that the AVDD and AVSS pins Parallel Port 1 specified in Figure 3 are inputs to the processor and not the ana- Total DMA Channels 25 log ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Rev. J | Page 8 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide