X9418 Datasheet (Renesas) - 9
| Manufacturer | Renesas |
| Description | Low Noise/Low Power/2-Wire Bus |
| Pages / Page | 20 / 9 — Wiper Counter Register, (6-Bit), Volatile. Instruction Format Notes:. … |
| Revision | 2.00 |
| File Format / Size | PDF / 841 Kb |
| Document Language | English |
Wiper Counter Register, (6-Bit), Volatile. Instruction Format Notes:. Read Wiper Counter Register (WCR)
Model Line for this Datasheet
Text Version of Document
X9418
Wiper Counter Register, (6-Bit), Volatile
One 6-bit wiper counter register for each XDCP. (Four 6- bit registers in total.) WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V – {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is (MSB) (LSB) loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR.
Instruction Format Notes:
(1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type device instruction WCR wiper position S S M S T identifier addresses opcode addresses (sent by slave on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A 3 2 1 0 K 1 0 0 1 0 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
S device type device instruction WCR wiper position S S S S T identifier addresses opcode addresses (sent by master on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A 3 2 1 0 K 1 0 1 0 0 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Read Data Register (DR)
S device type device instruction DR and WCR wiper position/data S S M S T identifier addresses opcode addresses (sent by slave on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A R 3 2 1 0 K 1 0 1 1 R 1 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Write Data Register (DR)
S device type device instruction DR and WCR wiper position/data S S S S T identifier addresses opcode addresses (sent by master on SDA) A A A T HIGH-VOLTAGE A C C W W W W W W C O WRITE CYCLE R 0 1 0 1 A A A A R 3 2 1 0 K 1 1 0 0 R 1 0 0 P0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type device instruction DR and WCR S S S T identifier addresses opcode addresses A A T A C C O R 0 1 0 1 A A A A R 3 2 1 0 K 1 1 0 1 R 1 0 0 P 0 K P T FN8194 Rev 2.00 Page 9 of 20 October 12, 2006
Wiper Counter Register, (6-Bit), Volatile
One 6-bit wiper counter register for each XDCP. (Four 6- bit registers in total.) WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V – {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is (MSB) (LSB) loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR.
Instruction Format Notes:
(1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type device instruction WCR wiper position S S M S T identifier addresses opcode addresses (sent by slave on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A 3 2 1 0 K 1 0 0 1 0 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
S device type device instruction WCR wiper position S S S S T identifier addresses opcode addresses (sent by master on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A 3 2 1 0 K 1 0 1 0 0 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Read Data Register (DR)
S device type device instruction DR and WCR wiper position/data S S M S T identifier addresses opcode addresses (sent by slave on SDA) A A A T A C C W W W W W W C O R 0 1 0 1 A A A A R 3 2 1 0 K 1 0 1 1 R 1 0 0 P 0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
Write Data Register (DR)
S device type device instruction DR and WCR wiper position/data S S S S T identifier addresses opcode addresses (sent by master on SDA) A A A T HIGH-VOLTAGE A C C W W W W W W C O WRITE CYCLE R 0 1 0 1 A A A A R 3 2 1 0 K 1 1 0 0 R 1 0 0 P0 K 0 0 P P P P P P K P T 5 4 3 2 1 0
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type device instruction DR and WCR S S S T identifier addresses opcode addresses A A T A C C O R 0 1 0 1 A A A A R 3 2 1 0 K 1 1 0 1 R 1 0 0 P 0 K P T FN8194 Rev 2.00 Page 9 of 20 October 12, 2006
