Datasheet Si8935/36/37 (Silicon Labs) - 8
| Manufacturer | Silicon Labs |
| Description | Delta-Sigma Modulator for Voltage Measurement |
| Pages / Page | 25 / 8 — Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Digital. … |
| Revision | 0.1 |
| File Format / Size | PDF / 471 Kb |
| Document Language | English |
Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Digital. External Clock (Si8935). Internal Clock (Si8936). Internal Clock (Si8937)
Model Line for this Datasheet
Text Version of Document
Si8935/36/37 Data Sheet Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Units
PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 mV –100 dB Power-Supply Re- and 10 kHz ripple PSRR jection Ratio PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 mV –100 dB and 10 kHz ripple
Digital
Logic high input V 70% of V threshold IH VDDB Logic low input V 20% of V threshold IL VDDB Input hysteresis VIHYST 120 mV Output load C capacitance LOAD 15 pF
External Clock (Si8935)
Clock Frequency FCLKIN 5 25 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 23 ns Data Hold Time THOLD 6 ns
Internal Clock (Si8936)
TA = 25 °C 9.9 10 10.1 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 9.8 10 10.2 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 60 ns Data Hold Time THOLD 40 ns
Internal Clock (Si8937)
TA = 25 °C 19.8 20 20.2 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 19.6 20 20.4 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 30 ns Data Hold Time THOLD 20 ns
Note:
1. An analog CMTI failure is defined as an output error of more than 100 mV persisting for at least 1 µs.
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 8 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History
Parameter Symbol Test Condition Min Typ Max Units
PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 mV –100 dB Power-Supply Re- and 10 kHz ripple PSRR jection Ratio PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 mV –100 dB and 10 kHz ripple
Digital
Logic high input V 70% of V threshold IH VDDB Logic low input V 20% of V threshold IL VDDB Input hysteresis VIHYST 120 mV Output load C capacitance LOAD 15 pF
External Clock (Si8935)
Clock Frequency FCLKIN 5 25 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 23 ns Data Hold Time THOLD 6 ns
Internal Clock (Si8936)
TA = 25 °C 9.9 10 10.1 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 9.8 10 10.2 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 60 ns Data Hold Time THOLD 40 ns
Internal Clock (Si8937)
TA = 25 °C 19.8 20 20.2 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 19.6 20 20.4 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 30 ns Data Hold Time THOLD 20 ns
Note:
1. An analog CMTI failure is defined as an output error of more than 100 mV persisting for at least 1 µs.
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 8 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History
