Datasheet TDC-GPX2 (AustriaMicroSystems) - 5
| Manufacturer | AustriaMicroSystems |
| Description | Time-to-Digital Converter High-end multipurpose 4-channel converter |
| Pages / Page | 77 / 5 — TDC-GPX2 −. Pin Description. Figure 5: Pin Description of TDC-GPX2. Pin … |
| Revision | 1-03 |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
TDC-GPX2 −. Pin Description. Figure 5: Pin Description of TDC-GPX2. Pin No. Pin Name. Description. Type. Not Used. ams Datasheet. Page 5
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Text Version of Document
TDC-GPX2 −
Pin Assignments
Pin Description Figure 5: Pin Description of TDC-GPX2 Pin No. Pin Name Description Type Not Used
1 FRAME1N Negative frame signal of stop channel 1 LVDS Output Open 2 FRAME1P Positive frame signal of stop channel 1 LVDS Output Open 3 SDO1N Negative serial data output of stop channel 1 LVDS Output Open 4 SDO1P Positive serial data output of stop channel 1 LVDS Output Open 5 FRAME2N Negative frame signal of stop channel 2 LVDS Output Open 6 FRAME2P Positive frame signal of stop channel 2 LVDS Output Open 7 SDO2N Negative serial data output of stop channel 2 LVDS Output Open 8 SDO2P Positive serial data output of stop channel 2 LVDS Output Open 9 FRAME3N Negative frame signal of stop channel 3 LVDS Output Open 10 FRAME3P Positive frame signal of stop channel 3 LVDS Output Open 11 SDO3N Negative serial data output of stop channel 3 LVDS Output Open 12 SDO3P Positive serial data output of stop channel 3 LVDS Output Open 13 FRAME4N Negative frame signal of stop channel 4 LVDS Output Open 14 FRAME4P Positive frame signal of stop channel 4 LVDS Output Open 15 SDO4N Negative serial data output of stop channel 4 LVDS Output Open 16 SDO4P Positive serial data output of stop channel 4 LVDS Output Open 17 LCLKOUTN Negative serial clock output LVDS Output Open 18 LCLKOUTP Positive serial clock output LVDS Output Open 19, 21, 62 DGND Ground for digital and IO units Power Supply 20, 61 DVDD33 3.3V supply for digital and IO units Power Supply 22, 60 DVDD18 1.8V supply for digital and IO units Power Supply 23 RVDD33 3.3V supply for linear voltage regulator Power Supply 24 DVDD18O 1.8V supply voltage for digital and IO units Regulator Out Open 25 TVDD18O 1.8V supply voltage for time frontend Regulator Out Open 26 CVDD18O 1.8V supply voltage for time digital converter Regulator Out Open 27 RGND Ground for linear voltage regulator Power Supply 28 CGND Ground for TDC Power Supply
ams Datasheet Page 5
[v1-03] 2017-Dec-18 Document Feedback Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide
Pin Assignments
Pin Description Figure 5: Pin Description of TDC-GPX2 Pin No. Pin Name Description Type Not Used
1 FRAME1N Negative frame signal of stop channel 1 LVDS Output Open 2 FRAME1P Positive frame signal of stop channel 1 LVDS Output Open 3 SDO1N Negative serial data output of stop channel 1 LVDS Output Open 4 SDO1P Positive serial data output of stop channel 1 LVDS Output Open 5 FRAME2N Negative frame signal of stop channel 2 LVDS Output Open 6 FRAME2P Positive frame signal of stop channel 2 LVDS Output Open 7 SDO2N Negative serial data output of stop channel 2 LVDS Output Open 8 SDO2P Positive serial data output of stop channel 2 LVDS Output Open 9 FRAME3N Negative frame signal of stop channel 3 LVDS Output Open 10 FRAME3P Positive frame signal of stop channel 3 LVDS Output Open 11 SDO3N Negative serial data output of stop channel 3 LVDS Output Open 12 SDO3P Positive serial data output of stop channel 3 LVDS Output Open 13 FRAME4N Negative frame signal of stop channel 4 LVDS Output Open 14 FRAME4P Positive frame signal of stop channel 4 LVDS Output Open 15 SDO4N Negative serial data output of stop channel 4 LVDS Output Open 16 SDO4P Positive serial data output of stop channel 4 LVDS Output Open 17 LCLKOUTN Negative serial clock output LVDS Output Open 18 LCLKOUTP Positive serial clock output LVDS Output Open 19, 21, 62 DGND Ground for digital and IO units Power Supply 20, 61 DVDD33 3.3V supply for digital and IO units Power Supply 22, 60 DVDD18 1.8V supply for digital and IO units Power Supply 23 RVDD33 3.3V supply for linear voltage regulator Power Supply 24 DVDD18O 1.8V supply voltage for digital and IO units Regulator Out Open 25 TVDD18O 1.8V supply voltage for time frontend Regulator Out Open 26 CVDD18O 1.8V supply voltage for time digital converter Regulator Out Open 27 RGND Ground for linear voltage regulator Power Supply 28 CGND Ground for TDC Power Supply
ams Datasheet Page 5
[v1-03] 2017-Dec-18 Document Feedback Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide
