Datasheet EFR32MG21 (Silicon Labs) - 8

ManufacturerSilicon Labs
DescriptionMighty Gecko Multiprotocol Wireless SoC Family
Pages / Page75 / 8 — 3.3 General Purpose Input/Output (GPIO). 3.4 Clocking. 3.4.1 Clock …
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3.3 General Purpose Input/Output (GPIO). 3.4 Clocking. 3.4.1 Clock Management Unit (CMU)

3.3 General Purpose Input/Output (GPIO) 3.4 Clocking 3.4.1 Clock Management Unit (CMU)

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link to page 64 link to page 13 EFR32MG21 Mighty Gecko Multiprotocol Wireless SoC Family Data Sheet System Overview
3.3 General Purpose Input/Output (GPIO)
EFR32MG21 has up to 20 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher- als. The GPIO subsystem supports asynchronous external pin interrupts. All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon which internal peripherals could once again drive those pads. A few GPIOs also have EM4 wake functionality. These pins are listed in 6.2 Alternate Function Table.
3.4 Clocking 3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32MG21. Individual enabling and disabling of clocks to all periph- eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators.
3.4.2 Internal and External Oscillators
The EFR32MG21 supports two crystal oscillators and fully integrates five RC oscillators, listed below. • A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer- ence for the MCU and RF synthesizer. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO can also support an external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature. • A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes. • An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 80 MHz. • An integrated high frequency RC oscillator (HFRCOEM2) runs down to EM2 and is available for timing the general-purpose ADC and the Serial Wire Viewer port with a wide frequency range. • An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz • An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation where high accuracy is not required. • An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con- sumption in low energy modes.
3.5 Counters/Timers and PWM 3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers. In addition some timers offer dead-time insertion. See 3.12 Configuration Summary for information on the feature set of each timer.
3.5.2 Low Energy Timer (LETIMER)
The unique LETIMER is a 24-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave- forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to start counting on compare matches from other peripherals such as the RTC.
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| Building a more connected world. Rev. 1.0 | 8 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Radio 3.2.1 Antenna Interface 3.2.2 Fractional-N Frequency Synthesizer 3.2.3 Receiver Architecture 3.2.4 Transmitter Architecture 3.2.5 Packet and State Trace 3.2.6 Data Buffering 3.2.7 Radio Controller (RAC) 3.3 General Purpose Input/Output (GPIO) 3.4 Clocking 3.4.1 Clock Management Unit (CMU) 3.4.2 Internal and External Oscillators 3.5 Counters/Timers and PWM 3.5.1 Timer/Counter (TIMER) 3.5.2 Low Energy Timer (LETIMER) 3.5.3 Real Time Clock with Capture (RTCC) 3.5.4 Back-Up Real Time Counter 3.5.5 Watchdog Timer (WDOG) 3.6 Communications and Other Digital Peripherals 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.6.2 Inter-Integrated Circuit Interface (I2C) 3.6.3 Peripheral Reflex System (PRS) 3.7 Security Features 3.7.1 Standard Security 3.7.2 True Random Number Generator 3.8 Analog 3.8.1 Analog Comparator (ACMP) 3.8.2 Analog to Digital Converter (ADC) 3.9 Reset Management Unit (RMU) 3.10 Core and Memory 3.10.1 Processor Core 3.10.2 Memory System Controller (MSC) 3.10.3 Linked Direct Memory Access Controller (LDMA) 3.11 Memory Map 3.12 Configuration Summary 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Absolute Maximum Ratings 4.1.2 General Operating Conditions 4.1.3 Thermal Characteristics 4.1.4 Current Consumption 4.1.4.1 MCU current consumption at 1.8V 4.1.4.2 MCU current consumption at 3.0V 4.1.4.3 Radio current consumption at 1.8V 4.1.4.4 Radio current consumption at 3.0V 4.1.5 2.4 GHz RF Transceiver Characteristics 4.1.5.1 RF Transmitter Characteristics 4.1.5.2 RF Receiver Characteristics 4.1.6 Flash Characteristics 4.1.7 Wake Up, Entry, and Exit times 4.1.8 Oscillators 4.1.8.1 High Frequency Crystal Oscillator 4.1.8.2 Low Frequency Crystal Oscillator 4.1.8.3 High Frequency RC Oscillator (HFRCO) 4.1.8.4 Fast Start_Up RC Oscillator (FSRCO) 4.1.8.5 Low Frequency RC Oscillator 4.1.8.6 Ultra Low Frequency RC Oscillator 4.1.9 GPIO Pins (3V GPIO pins) 4.1.10 Analog to Digital Converter (ADC) 4.1.11 Analog Comparator (ACMP) 4.1.12 Temperature Sense 4.1.13 Brown Out Detectors 4.1.13.1 DVDD BOD 4.1.13.2 LE DVDD BOD 4.1.13.3 AVDD and VIO BODs 4.1.14 SPI Electrical Specifications 4.1.14.1 SPI Master Timing 4.1.14.2 SPI Slave Timing 4.1.15 I2C Electrical Specifications 4.1.15.1 I2C Standard-mode (Sm) 4.1.15.2 I2C Fast-mode (Fm) 4.1.15.3 I2C Fast-mode Plus (Fm+) 4.2 Typical Performance Curves 4.2.1 Supply Current 4.2.2 2.4 GHz Radio 5. Typical Connection Diagrams 5.1 Power 5.2 RF Matching Networks 5.2.1 2.4 GHz 0 dBm Matching Network 5.2.2 2.4 GHz 10 dBm Matching Network 5.2.3 2.4 GHz 20 dBm Matching Network 5.3 Other Connections 6. Pin Definitions 6.1 QFN32 2.4GHz Device Pinout 6.2 Alternate Function Table 6.3 Analog Peripheral Connectivity 6.4 Digital Peripheral Connectivity 7. QFN32 Package Specifications 7.1 QFN32 Package Dimensions 7.2 QFN32 PCB Land Pattern 7.3 QFN32 Package Marking 8. Revision History