Datasheet L5965 (STMicroelectronics) - 10
| Manufacturer | STMicroelectronics |
| Description | Multiple power management for automotive vision and radar systems |
| Pages / Page | 85 / 10 — L5965. Electrical characteristics. Symbol. Parameter. Test condition. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
L5965. Electrical characteristics. Symbol. Parameter. Test condition. Min. Typ. Max. Unit. BUCK1 GATE Driver. BUCK2. DS12567. Rev 2. page 10/85
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L5965 Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit
SPI = 000 default – 50 – ns SPI = 001 – 40 – ns SPI = 010 – 30 – ns SPI = 011 – 0 – ns t Dead time (Blanktime: non-overlap time programming_dead_BUCK1 plus programming time) SPI = 100 – 60 – ns SPI = 101 – 70 – ns SPI = 110 – 100 – ns SPI = 111 – 200 – ns ton_min – – – 208 – ns
BUCK1 GATE Driver
SPI = '0' (1.0 A) – 1.75 – Ω Ron HS1 Ron @ Buck1_curr_max SPI = '1' (2.0 A) – 0.85 – Ω SPI = '0' (1.0 A) – 3.20 – Ω Ron LS1 Ron @ Buck1_curr_max SPI = '1' (2.0 A) – 1.60 – Ω V Clamp protection for Vgs of external CLAMP_VGS_HS – 9 – 11 V transistor V Clamp protection for Vgs of external CLAMP_VGS_LS – 9 – 11 V transistor SPI = 00 0.3 0.42 0.55 ms t Soft start time when start up, Vref from 0 V SOFTSTART_BUCK1 SPI = 01 0.7 1 1.3 ms to 1 V SPI = 10 1.6 2 2.4 ms
BUCK2
VIN_BUCK2 Input voltage range – 3.3 – 32 V OTP = 000 5.0 V OTP = 001 3.6 V OTP = 010 3.3 V OTP = 011 1.5 V V +2.5 OUT_BUCK2 Output voltage (no load, static) -2.5% % OTP = 100 1.35 V OTP = 101 1.2 V OTP = 110 1.1 V OTP = 111 1.0 V ton_min Min Ton internal FET – – 100 – ns OTP = 0 0.34 0.4 0.46 MHz FSW Free running frequency OTP = 1 2.04 2.4 2.76 MHz Load = 0.3 A to 1.8 A, ∆t = 10 µs, ∆V (2) BUCK2/VBUCK2 Undershoot &overshoot VIN = 5 V -5 – 5 % VIN = 6 V to 32 V, VOUT = 5 V ∆VLINER-LOADR_VBUCK2 Static line + load regulation – -0.45 – % ILoad = 0.3 A to 1.8 A OTP = 0 1.35 1.8 2.3 A ILIMIT Peak switching current limitation OTP = 1 2.6 3.4 4.2 A RonHS High side switch on resistance – – 120 190 mΩ
DS12567
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Rev 2 page 10/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history
L5965 Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit
SPI = 000 default – 50 – ns SPI = 001 – 40 – ns SPI = 010 – 30 – ns SPI = 011 – 0 – ns t Dead time (Blanktime: non-overlap time programming_dead_BUCK1 plus programming time) SPI = 100 – 60 – ns SPI = 101 – 70 – ns SPI = 110 – 100 – ns SPI = 111 – 200 – ns ton_min – – – 208 – ns
BUCK1 GATE Driver
SPI = '0' (1.0 A) – 1.75 – Ω Ron HS1 Ron @ Buck1_curr_max SPI = '1' (2.0 A) – 0.85 – Ω SPI = '0' (1.0 A) – 3.20 – Ω Ron LS1 Ron @ Buck1_curr_max SPI = '1' (2.0 A) – 1.60 – Ω V Clamp protection for Vgs of external CLAMP_VGS_HS – 9 – 11 V transistor V Clamp protection for Vgs of external CLAMP_VGS_LS – 9 – 11 V transistor SPI = 00 0.3 0.42 0.55 ms t Soft start time when start up, Vref from 0 V SOFTSTART_BUCK1 SPI = 01 0.7 1 1.3 ms to 1 V SPI = 10 1.6 2 2.4 ms
BUCK2
VIN_BUCK2 Input voltage range – 3.3 – 32 V OTP = 000 5.0 V OTP = 001 3.6 V OTP = 010 3.3 V OTP = 011 1.5 V V +2.5 OUT_BUCK2 Output voltage (no load, static) -2.5% % OTP = 100 1.35 V OTP = 101 1.2 V OTP = 110 1.1 V OTP = 111 1.0 V ton_min Min Ton internal FET – – 100 – ns OTP = 0 0.34 0.4 0.46 MHz FSW Free running frequency OTP = 1 2.04 2.4 2.76 MHz Load = 0.3 A to 1.8 A, ∆t = 10 µs, ∆V (2) BUCK2/VBUCK2 Undershoot &overshoot VIN = 5 V -5 – 5 % VIN = 6 V to 32 V, VOUT = 5 V ∆VLINER-LOADR_VBUCK2 Static line + load regulation – -0.45 – % ILoad = 0.3 A to 1.8 A OTP = 0 1.35 1.8 2.3 A ILIMIT Peak switching current limitation OTP = 1 2.6 3.4 4.2 A RonHS High side switch on resistance – – 120 190 mΩ
DS12567
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Rev 2 page 10/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history
