Datasheet A80603, A80603-1 (Allegro) - 6
Manufacturer | Allegro |
Description | LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple |
Pages / Page | 30 / 6 — A80603 and. LED Driver with Pre-Emptive Boost. A80603-1 for Ultra-High … |
File Format / Size | PDF / 4.6 Mb |
Document Language | English |
A80603 and. LED Driver with Pre-Emptive Boost. A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple
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A80603 and LED Driver with Pre-Emptive Boost A80603-1 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1]: Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indicates specifica- tions guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE SPECIFICATIONS
Operating Input Voltage Range [3] VIN ● 4.5 − 40 V VIN UVLO Start Threshold VUVLO(rise) VIN rising ● − – 4.35 V VIN UVLO Stop Threshold VUVLO(fall) VIN falling ● − – 3.95 V UVLO Hysteresis [2] VUVLO_HYS 300 450 600 mV
INPUT CURRENTS
VIN Pin Operating Current IOP EN and PWM = H, fSW = 2 MHz ● − 13 18 mA VIN Pin Quiescent Current IQ EN = H and PWM = L, fCLKOUT = 2 MHz ● − 10 − mA VIN Pin Sleep Current IQSLEEP VIN = 16 V, VEN = 0 V ● − 2 10 µA
INPUT LOGIC LEVELS (EN, PWM, APWM)
Input Logic Level-Low VIL ● − − 0.4 V Input Logic Level-High VIH ● 1.5 − − V Input Pull-Down Resistor REN, RPWM, R Input = 5 V 60 100 140 kΩ APWM
OUTPUT LOGIC LEVELS (CLKOUT)
Output Logic Level-Low VOL 5 V < VIN < 40 V ● − − 0.3 V Output Logic Level-High VOH 5 V < VIN < 40 V ● 1.8 − − V CLKOUT Duty Cycle DCLKOUT fSW = 2 MHz, no external sync ● 33 50 67 % CLKOUT Negative Pulse Width [2] tCLKNPW External sync = 260 kHz to 2.3 MHz − 200 − ns
APWM PIN
APWM Frequency Range [2] fAPWM Clock signal applied to pin ● 40 − 1000 kHz APWM Duty Cycle Range [2] DAPWM Clock signal applied to pin ● 0 − 90 %
VDD REGULATOR
Regulator Output Voltage VDD VIN > 4.5 V, iLOAD < 1 mA 4.05 4.25 4.45 V VDD UVLO Start Threshold VDDUVLOrise VDD rising, no external load − 3.2 − V VDD UVLO Stop Threshold VDDUVLOfall VDD falling, no external load − 2.65 − V
ERROR AMPLIFIER
Amplifier Gain [2] gm VCOMP = 1.5 V − 1000 − μA/V Source Current IEA(SRC) VCOMP = 1.5 V − –500 − μA Sink Current IEA(SINK) VCOMP = 1.5 V − +500 − μA COMP Pin Pull Down Resistance RCOMP FAULT = 0, VCOMP = 1.5 V − 1.4 − kΩ Continued on the next page… Allegro MicroSystems, LLC 6 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Selection Guide Absolute Maximum Ratings Thermal Characteristics Typical Application – SEPIC Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Functional Description Enabling the IC Powering Up: LED Detection Phase Powering Up: Boost Output Undervoltage Soft Start Function Frequency Selection Synchronization Loss of External Sync Signal Switching Frequency Dithering Clock Out Function LED Current Setting PWM Dimming Pre-Emptive Boost (PEB) Analog Dimming with APWM Pin Extending LED Dimming Ratio Analog Dimming with External Voltage VDD Shutdown Fault Detection and Protection LED String Partial-Short Detect Overvoltage Protection Boost Switch Overcurrent Protection Input Overcurrent Protection and Disconnect Switch Setting the Current Sense Resistor Input UVLO Fault Protection During Operation Fault Recovery Mechanism Package Outline Drawing