Datasheet LTC2358-16 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range |
| Pages / Page | 40 / 6 — POWER REQUIREMENTS The. denotes the specifications which apply over the … |
| Revision | A |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
POWER REQUIREMENTS The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2358-16
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (CL = 25pF) l 1.7 2.6 mA Acquisition or Nap Mode l 1 20 μA Power Down Mode l 1 20 μA PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 219 259 mW Acquisition Mode l 258 308 mW Nap Mode l 94 114 mW Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW Power Down Mode (H-Grade) l 0.68 3 mW
LVDS I/O Mode
OVDD Supply Voltage l 2.375 5.25 V IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled l 18.4 20.7 mA 200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 15) l 16.8 19.2 mA Acquisition Mode l 3.7 4.5 mA Nap Mode l 3.4 4.1 mA Power Down Mode (C-Grade and I-Grade) l 106 275 μA Power Down Mode (H-Grade) l 106 500 µA IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (RL = 100Ω) l 7 8.5 mA Acquisition or Nap Mode (RL = 100Ω) l 7 8.0 mA Power Down Mode l 1 20 μA PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 245 287 mW Acquisition Mode l 284 337 mW Nap Mode l 120 143 mW Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW Power Down Mode (H-Grade) l 0.68 3 mW
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency 8 Channels Enabled l 200 ksps 7 Channels Enabled l 225 ksps 6 Channels Enabled l 250 ksps 5 Channels Enabled l 300 ksps 4 Channels Enabled l 350 ksps 3 Channels Enabled l 425 ksps 2 Channels Enabled l 550 ksps 1 Channel Enabled l 800 ksps tCYC Time Between Conversions 8 Channels Enabled, fSMPL = 200ksps l 5000 ns 7 Channels Enabled, fSMPL = 225ksps l 4444 ns 6 Channels Enabled, fSMPL = 250ksps l 4000 ns 5 Channels Enabled, fSMPL = 300ksps l 3333 ns 4 Channels Enabled, fSMPL = 350ksps l 2855 ns 3 Channels Enabled, fSMPL = 425ksps l 2350 ns 2 Channels Enabled, fSMPL = 550ksps l 1815 ns 1 Channel Enabled, fSMPL = 800ksps l 1250 ns tCONV Conversion Time N Channels Enabled, 1 ≤ N ≤ 8 l 450•N 500•N 550•N ns tACQ Acquisition Time 8 Channels Enabled, fSMPL = 200ksps l 570 980 ns (tACQ = tCYC – tCONV – tBUSYLH) 7 Channels Enabled, fSMPL = 225ksps l 564 924 ns 6 Channels Enabled, fSMPL = 250ksps l 670 980 ns 5 Channels Enabled, fSMPL = 300ksps l 553 813 ns 4 Channels Enabled, fSMPL = 350ksps l 625 835 ns 3 Channels Enabled, fSMPL = 425ksps l 670 830 ns 2 Channels Enabled, fSMPL = 550ksps l 685 795 ns 1 Channel Enabled, fSMPL = 800ksps l 670 730 ns Rev A 6 For more information www.analog.com Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (CL = 25pF) l 1.7 2.6 mA Acquisition or Nap Mode l 1 20 μA Power Down Mode l 1 20 μA PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 219 259 mW Acquisition Mode l 258 308 mW Nap Mode l 94 114 mW Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW Power Down Mode (H-Grade) l 0.68 3 mW
LVDS I/O Mode
OVDD Supply Voltage l 2.375 5.25 V IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled l 18.4 20.7 mA 200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 15) l 16.8 19.2 mA Acquisition Mode l 3.7 4.5 mA Nap Mode l 3.4 4.1 mA Power Down Mode (C-Grade and I-Grade) l 106 275 μA Power Down Mode (H-Grade) l 106 500 µA IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (RL = 100Ω) l 7 8.5 mA Acquisition or Nap Mode (RL = 100Ω) l 7 8.0 mA Power Down Mode l 1 20 μA PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 245 287 mW Acquisition Mode l 284 337 mW Nap Mode l 120 143 mW Power Down Mode (C-Grade and I-Grade) l 0.68 1.9 mW Power Down Mode (H-Grade) l 0.68 3 mW
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency 8 Channels Enabled l 200 ksps 7 Channels Enabled l 225 ksps 6 Channels Enabled l 250 ksps 5 Channels Enabled l 300 ksps 4 Channels Enabled l 350 ksps 3 Channels Enabled l 425 ksps 2 Channels Enabled l 550 ksps 1 Channel Enabled l 800 ksps tCYC Time Between Conversions 8 Channels Enabled, fSMPL = 200ksps l 5000 ns 7 Channels Enabled, fSMPL = 225ksps l 4444 ns 6 Channels Enabled, fSMPL = 250ksps l 4000 ns 5 Channels Enabled, fSMPL = 300ksps l 3333 ns 4 Channels Enabled, fSMPL = 350ksps l 2855 ns 3 Channels Enabled, fSMPL = 425ksps l 2350 ns 2 Channels Enabled, fSMPL = 550ksps l 1815 ns 1 Channel Enabled, fSMPL = 800ksps l 1250 ns tCONV Conversion Time N Channels Enabled, 1 ≤ N ≤ 8 l 450•N 500•N 550•N ns tACQ Acquisition Time 8 Channels Enabled, fSMPL = 200ksps l 570 980 ns (tACQ = tCYC – tCONV – tBUSYLH) 7 Channels Enabled, fSMPL = 225ksps l 564 924 ns 6 Channels Enabled, fSMPL = 250ksps l 670 980 ns 5 Channels Enabled, fSMPL = 300ksps l 553 813 ns 4 Channels Enabled, fSMPL = 350ksps l 625 835 ns 3 Channels Enabled, fSMPL = 425ksps l 670 830 ns 2 Channels Enabled, fSMPL = 550ksps l 685 795 ns 1 Channel Enabled, fSMPL = 800ksps l 670 730 ns Rev A 6 For more information www.analog.com Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
