Datasheet ADAR7251 (Analog Devices) - 9

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Data Sheet ADAR7251 Limit at Parameter Description Min Typ Max Unit
ADC SERIAL PORT MASTER See Figure 3 MODE tSCKH SCLK_ADC high, slave mode 10 ns tSCKL SCLK_ADC low, slave mode 10 ns tDS ADC_DOUTx setup to SCLK_ADC rising, slave mode 10 ns tDH ADC_DOUTx hold from SCLK_ADC rising, slave mode 5 ns tDD ADC_DOUTx delay from SCLK_ADC falling 18 ns tFSH FS_ADC hold from SCLK_ADC rising 18 ns tFSS FS_ADC setup from SCLK_ADC falling 1 ns ADC SERIAL PORT SLAVE MODE See Figure 4 tSCKH SCLK_ADC high, slave mode 7 ns tSCKL SCLK_ADC low, slave mode 7 ns tDS ADC_DOUTx valid to SCLK_ADC rising, slave mode 11 ns tDH ADC_DOUTx hold from SCLK_ADC rising, slave mode 11 ns tDD ADC_DOUTx delay from SCLK_ADC falling 2 ns tFSH FS_ADC hold from SCLK_ADC rising 1 ns tFSS FS_ADC setup from SCLK_ADC falling 1 ns PARALLEL MODE, BYTE WIDE See Figure 5; if usingCONV_START, see Figure 6 for the FORMAT CONV_START to DATA_READY timing relation tSCKH SCLK_ADC high, master mode 28 ns tSCKL SCLK_ADC low, master mode 28 ns tDS ADC_DOUTx setup to SCLK_ADC rising, master mode 7 ns tDH ADC_DOUTx hold from SCLK_ADC rising, master mode 5 ns tDD ADC_DOUTx delay from SCLK_ADC falling for left justified (LJ) mode 6 ns For I2S mode, add one SCLK_ADC period to the tDD of LJ mode tCSDR CONV_START falling to DATA_READY rising 1.215 μs DATA ACQUISITION (DAQ) CONV_START falling to DATA_READY rising, see Figure 6 MODE tDRH CONV_START rising to DATA_READY falling 0.44 μs tCSDR DAQ16 mode (16 acquisition clock cycles) 1.215 μs DAQ24 mode (24 acquisition clock cycles) 1.8 μs DAQ32 mode (32 acquisition clock cycles) 2.43 μs
Timing Diagrams tCLS tCLH tCLPH tCCPL SPI_SS tCCPH SPI_SCLK SPI_MOSI tCDH t t CDH CDS tCOTS SPI_MISO
02 0
t
57-
COD
123 Figure 2. SPI Port Timing Rev. 0 | Page 9 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products