Datasheet ADL5335 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 700 MHz to 4200 MHz Tx DGA |
| Pages / Page | 16 / 3 — Data Sheet. ADL5335. SPECIFICATIONS. Table 1. Parameter. Test … |
| File Format / Size | PDF / 525 Kb |
| Document Language | English |
Data Sheet. ADL5335. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
Data Sheet ADL5335 SPECIFICATIONS
VPOS1, VPOS2, VPOS3 = 5 V, TA = 25°C, impedance out (ZOUT) = 50 Ω, and a differential input drive, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Input Frequency Range 700 4200 MHz Impedance Input Differential input drive 50 Ω Output Single-ended output 50 Ω GAIN CONTROL Gain Range 20 dB Maximum Gain 12.0 dB Minimum Gain −8.0 dB Gain Step Size 0.5 dB BAND 8: 925 MHz TO 960 MHz Gain Range 20 dB Maximum Gain 13.0 dB Minimum Gain −7.0 dB Gain Flatness ±200 MHz, all gains 0.3 dB Gain Step Error All gain states 0.2 dB Group Delay Variation Between any attenuation step 50 ps Output Third-Order Intercept (IP3) Maximum gain, 4 dBm per tone 34 dBm Minimum gain, −18 dBm per tone 13.6 dBm Output 1 dB Compression Point (P1dB) Maximum gain 18.0 dBm Minimum gain −0.6 dBm Noise Figure Maximum gain 5.4 dB Minimum gain 8.3 dB Return Loss Input −18 dB Output Minimum gain −17 dB Maximum gain −30 dB Common-Mode Rejection Ratio (CMRR) vs. frequency (±200 MHz) 20 dB BAND 3: 1805 MHz TO 1880 MHz Gain Range 20 dB Maximum Gain 12.8 dB Minimum Gain −7.2 dB Gain Flatness ±200 MHz, all gains 0.5 dB Gain Step Error All gain states 0.4 dB Group Delay Variation Between any attenuation step 45 ps Output IP3 Maximum gain, 4 dBm per tone 33 dBm Minimum gain, −18 dBm per tone 12 dBm Output P1dB Maximum gain 18.3 dBm Minimum gain 0 dBm Noise Figure Maximum gain 6.9 dB Minimum gain 10.6 dB Return Loss Input −32 dB Output Minimum gain −23 dB Maximum gain −17 dB CMRR vs. frequency (±200 MHz) 22 dB Rev. 0 | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DIGITAL LOGIC TIMING SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE DIGITAL INTERFACE OVERVIEW Serial Peripheral Interface (SPI) Fast Attack (FA) APPLICATIONS INFORMATION BASIC CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE
VPOS1, VPOS2, VPOS3 = 5 V, TA = 25°C, impedance out (ZOUT) = 50 Ω, and a differential input drive, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Input Frequency Range 700 4200 MHz Impedance Input Differential input drive 50 Ω Output Single-ended output 50 Ω GAIN CONTROL Gain Range 20 dB Maximum Gain 12.0 dB Minimum Gain −8.0 dB Gain Step Size 0.5 dB BAND 8: 925 MHz TO 960 MHz Gain Range 20 dB Maximum Gain 13.0 dB Minimum Gain −7.0 dB Gain Flatness ±200 MHz, all gains 0.3 dB Gain Step Error All gain states 0.2 dB Group Delay Variation Between any attenuation step 50 ps Output Third-Order Intercept (IP3) Maximum gain, 4 dBm per tone 34 dBm Minimum gain, −18 dBm per tone 13.6 dBm Output 1 dB Compression Point (P1dB) Maximum gain 18.0 dBm Minimum gain −0.6 dBm Noise Figure Maximum gain 5.4 dB Minimum gain 8.3 dB Return Loss Input −18 dB Output Minimum gain −17 dB Maximum gain −30 dB Common-Mode Rejection Ratio (CMRR) vs. frequency (±200 MHz) 20 dB BAND 3: 1805 MHz TO 1880 MHz Gain Range 20 dB Maximum Gain 12.8 dB Minimum Gain −7.2 dB Gain Flatness ±200 MHz, all gains 0.5 dB Gain Step Error All gain states 0.4 dB Group Delay Variation Between any attenuation step 45 ps Output IP3 Maximum gain, 4 dBm per tone 33 dBm Minimum gain, −18 dBm per tone 12 dBm Output P1dB Maximum gain 18.3 dBm Minimum gain 0 dBm Noise Figure Maximum gain 6.9 dB Minimum gain 10.6 dB Return Loss Input −32 dB Output Minimum gain −23 dB Maximum gain −17 dB CMRR vs. frequency (±200 MHz) 22 dB Rev. 0 | Page 3 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DIGITAL LOGIC TIMING SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE DIGITAL INTERFACE OVERVIEW Serial Peripheral Interface (SPI) Fast Attack (FA) APPLICATIONS INFORMATION BASIC CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE
