Datasheet AK5704 (Asahi Kasei Microdevices)
| Manufacturer | Asahi Kasei Microdevices |
| Description | Low-Power 4-ch 32-bit ADC with MIC-Amp |
| Pages / Page | 109 / 1 — AK5704. Low-Power 4-ch 32-bit ADC with MIC-Amp. 1. General Description. … |
| File Format / Size | PDF / 4.5 Mb |
| Document Language | English |
AK5704. Low-Power 4-ch 32-bit ADC with MIC-Amp. 1. General Description. 2. Features. Recording Function
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[AK5704]
AK5704 Low-Power 4-ch 32-bit ADC with MIC-Amp 1. General Description
The AK5704 is a high performance analog front-end AD converter IC ideal for voice recognition, voice control, and conferencing applications. The device has a built-in 4-ch 32-bit ADC and a low noise microphone amplifier and extracts full performance of a high S/N microphone with low power consumption by achieving dynamic range of 105dB. It is possible to support up to 16-ch microphone array by connecting multiple AK5704’s. In addition, since it incorporates ultra-low power consumption voice activity detection, power consumption during wait time is greatly reduced. The AK5704
2. Features 1. Recording Function
•
4-Channel Low Power 32-bit ADC 2-types Digital Filter (Low-latency [5/fs] Sharp Roll-off and Voice)
•
Single-ended Inputs or Full-differential Inputs
•
MIC Amplifier Gain: +30 dB to 0 dB, 3 dB step
•
2-output MIC Power Supplies: 2.8 V / 2.5 V / 1.8 V / Direct Mode Selectable
•
ADC Characteristics: S/N, DR: 105 dB, THD+N:
90 dB, (Gain = 0 dB) S/N, DR: 96 dB, THD+N:
86 dB, (Gain = +18 dB)
•
Excellent Power Supply Noise Reduction PSRR: 60dB Spurious Free Dynamic Range: 100dBc
•
4-Channel Digital MIC Interface
•
Programmable Phase Adjustment
•
Microphone Sensitivity Adjustment 2. Digital Voice Activity Detector 3. Programmable Digital Filter
•
Mixer
•
2nd order HPF and LPF
•
Digital ALC (Automatic Level Control): 4-ch Link Mode, 2-ch Mode 4. Digital Audio interface
•
Master/Slave mode
•
Sampling Frequency: 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 88.2 k, 96 k, 176.4 k, 192 kHz
•
Interface Format - 32/24/16-bit I2S/MSB justified, 16-bit PCM Short/Long Frame - 4-ch TDM - 8/12/16-ch Cascade TDM 5. Built-in PLL 6. Control I/F: I2C-bus (400kHz) 7. Operation Temperature Range: Ta =
40 to 85°C 8. Power Supply:
•
AVDD (ADC, MIC, PLL): 1.7 to 1.9 V or 3.0V to 3.6V
•
TVDD (Host & Audio I/F, LDO12): 1.65 to 3.6 V 9. Package: 28-pin QFN
019000890-E-00 2019/02 - 1 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE
AK5704 Low-Power 4-ch 32-bit ADC with MIC-Amp 1. General Description
The AK5704 is a high performance analog front-end AD converter IC ideal for voice recognition, voice control, and conferencing applications. The device has a built-in 4-ch 32-bit ADC and a low noise microphone amplifier and extracts full performance of a high S/N microphone with low power consumption by achieving dynamic range of 105dB. It is possible to support up to 16-ch microphone array by connecting multiple AK5704’s. In addition, since it incorporates ultra-low power consumption voice activity detection, power consumption during wait time is greatly reduced. The AK5704
2. Features 1. Recording Function
•
4-Channel Low Power 32-bit ADC 2-types Digital Filter (Low-latency [5/fs] Sharp Roll-off and Voice)
•
Single-ended Inputs or Full-differential Inputs
•
MIC Amplifier Gain: +30 dB to 0 dB, 3 dB step
•
2-output MIC Power Supplies: 2.8 V / 2.5 V / 1.8 V / Direct Mode Selectable
•
ADC Characteristics: S/N, DR: 105 dB, THD+N:
90 dB, (Gain = 0 dB) S/N, DR: 96 dB, THD+N:
86 dB, (Gain = +18 dB)
•
Excellent Power Supply Noise Reduction PSRR: 60dB Spurious Free Dynamic Range: 100dBc
•
4-Channel Digital MIC Interface
•
Programmable Phase Adjustment
•
Microphone Sensitivity Adjustment 2. Digital Voice Activity Detector 3. Programmable Digital Filter
•
Mixer
•
2nd order HPF and LPF
•
Digital ALC (Automatic Level Control): 4-ch Link Mode, 2-ch Mode 4. Digital Audio interface
•
Master/Slave mode
•
Sampling Frequency: 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 88.2 k, 96 k, 176.4 k, 192 kHz
•
Interface Format - 32/24/16-bit I2S/MSB justified, 16-bit PCM Short/Long Frame - 4-ch TDM - 8/12/16-ch Cascade TDM 5. Built-in PLL 6. Control I/F: I2C-bus (400kHz) 7. Operation Temperature Range: Ta =
40 to 85°C 8. Power Supply:
•
AVDD (ADC, MIC, PLL): 1.7 to 1.9 V or 3.0V to 3.6V
•
TVDD (Host & Audio I/F, LDO12): 1.65 to 3.6 V 9. Package: 28-pin QFN
019000890-E-00 2019/02 - 1 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE
