Datasheet AD9213 (Analog Devices)

12-Bit, 10.25 GSPS, JESD204B, RF Analog-to-Digital Converter Preliminary Technical Data AD9213 FEATURES
The AD9213 achieves industry leading dynamic range and
High instantaneous dynamic range
linearity performance while consuming only 5 W. Based on an
Noise spectral density 154 dBFS/Hz
interleaved pipeline architecture, the AD9213 features a
SFDR 70 dBc (1 GHz, −1 dBFS)
proprietary calibration and randomization technique that
Low power consumption: 5.1 W at 10 GSPS
suppresses interleaving spurious artifacts into its noise floor.
Integrated input buffer (6.5 GHz input bandwidth)
The excellent linearity performance of the AD9213 is preserved
1.4 V p-p full-scale input with RIN = 50 Ω
by a combination of on-chip dithering and calibration resulting
Overvoltage protection
in excellent spurious free performance over a wide range of
16-lane JESD204B output (up to 16 Gbps line rate)
input signal conditions.
Multichip sync capable with 1 sample accuracy
Applications requiring less instantaneous bandwidth can
DDC NCO synchronization included
benefit from the on-chip digital signal processing (DSP)
Fast overrange detection for efficient AGC
capability of the AD9213 that reduces the output data rate along
Integrated DDC
with the number of JESD204b lanes required to support it. The
Selectable decimation factors
DSP path includes a digital downconverter (DDC) with a 48-bit,
16-profile settings for fast frequency hopping
numerically controlled oscillator (NCO) followed by an I and Q
Optional on-chip PLL clock multiplier
digital decimator stage allowing for selectable decimation rates
On-chip temperature sensor
that are factors of two or three. For fast frequency hopping
On-chip negative voltage generators
applications, the AD9213 NCO supports up to 16-profile settings
Low CER <1e−16
with separate trigger input al owing for wide surveil ance frequency
12 mm × 12 mm BGA
coverage but at a reduced JESD204B lane count.
GENERAL DESCRIPTION
The AD9213 also supports sample accurate multichip The AD9213 is a single 12-bit, 10.25 GSPS, RF analog-to-digital synchronization that also includes synchronization of the converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 NCOs. The AD9213 will be offered in a 192 flip-chip ball grid has been optimized to support high dynamic range frequency array (FcBGA) package. The AD9213 is specified over a and time domain applications requiring wide instantaneous junction temperature range of −10°C to +115°C. bandwidth and low code error rates (CER). The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.
FUNCTIONAL BLOCK DIAGRAM AVDD2 AVDD1 DVDD JVDD2 JVDD1 (2.0V) (1.0V) AGND (1.0V) (2.0V) (1.0V) DIGITAL AVNN1 AD9213 GAIN ADJUST (–1.0V) R TS SERDOUT0± BUFFER U SERDOUT1± 16 VIN+ LIZE ADC 12 TP 16 D204B IA VIN– CORE DDC+ S R OU DEC-BY-N JE E SERDOUT15± I/Q S Tx VCM SIGNAL DGND MONITOR CLOCK JESD204B SYNCINB± DISTRIBUTION SUBCLASS 1 CONTROL SYSREF± CLK+ CLK– GPIO SPI TRIGGER CLK ASSIGNMENT CONTROL SYNTH SVDD2 (2.0V) CLKVDD CLKGND GPIO0, GPIO1 SDIO SCLK CSB
001
(1.0V) GPIO3, GPIO4, GPIO5
15030- Figure 1.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS