Datasheet AD9213 (Analog Devices) - 7

Preliminary Technical Data AD9213 Parameter Test Conditions/Comments Temperature1 Min Typ Max Unit
APERTURE Delay Full ps Uncertainty (Jitter) Full 50 fS rms Out-of-Range Recovery Time Full Clock cycles 1 Full temperature range is −10°C to +115°C junction temperature (Tj). Startup at a junction temperature of −40°C is guaranteed.All temperatures are junction temperatures. 2 SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising clock edge. Positive setup time leads the clock edge. Negative hold time also leads the clock edge.
TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK ns tDH Hold time between the data and the rising edge of SCLK ns tCLK Period of the SCLK ns tS Setup time between CSB and SCLK ns tH Hold time between CSB and SCLK ns tHIGH Minimum period that SCLK should be in a logic high state ns tLOW Minimum period that SCLK should be in a logic low state ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the ns SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the ns SCLK rising edge
Timing Diagrams CLK– CLK+ tSU_SR tH_SR SYSREF–
002
SYSREF+
15030- Figure 2. SYSREF± Setup and Hold Timing
tDS tHIGH tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
003
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
15030- Figure 3. Serial Port Interface Timing Diagram (MSB First) Rev. PrG | Page 7 of 97 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS