Datasheet AD9670 (Analog Devices) - 8

AD9670 Data Sheet SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, digital demodulator and baseband decimator bypassed, unless otherwise noted.
Table 3. Parameter1 Temperature Min Typ Max Unit
CLOCK2 Clock Rate 40 MSPS (Mode I) Full 20.5 40 MHz 65 MSPS (Mode II) Full 20.5 65 MHz 80 MSPS (Mode III)3 Full 20.5 80 MHz 125 MSPS (Mode IV)4 Full 20.5 125 MHz Clock Pulse Width High (tEH) Full 3.75 ns Clock Pulse Width Low (tEL) Full 3.75 ns OUTPUT PARAMETERS2, 5 Propagation Delay (tPD) Full 10.8 − 1.5 × tDCO 10.8 10.8 + 1.5 × tDCO ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps DCO Period (tDCO)6 Full tSAMPLE/7 ns FCO Propagation Delay (tFCO) Full 10.8 − 1.5 × tDCO 10.8 10.8 + 1.5 × tDCO ns DCO Propagation Delay (tCPD)7 Full tFCO + (tSAMPLE/28) ns DCO to Data Delay (tDATA)7 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)7 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Full ±225 ±400 ps TX_TRIG to CLK Setup Time (tSETUP) 25°C 1 ns TX_TRIG to CLK Hold Time (tHOLD) 25°C 1 ns Wake-Up Time Standby 25°C 2 μs Power-Down 25°C 375 μs ADC Pipeline Latency Full 16 Clock cycles APERTURE Aperture Uncertainty (Jitter) 25°C <1 ps rms LO GENERATION MLO8 Frequency 4LO Mode Full 4 40 MHz 8LO Mode Full 8 80 MHz 16LO Mode Full 16 160 MHz RESET9 to MLO Setup Time (t 10 SETUP) Full 1 tMLO /2 ns RESET to MLO Hold Time (t 10 HOLD) Full 1 tMLO /2 ns 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 The clock can be adjusted via the SPI. 3 Mode III must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS. 4 Mode IV must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS. 5 Measurements were taken using a device soldered to FR-4 material. 6 In the typical value, tSAMPLE/7, 7 is based on the number of bits (14) divided by 2 because the interface uses double data rate (DDR) sampling. 7 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 8 MLO refers to the differential signal created via the MLO− pin and the MLO+ pin. This notation is used throughout the data sheet. 9 RESET refers to the differential signal created via the RESET− pin and the RESET+ pin. This notation is used throughout the data sheet. 10 The period of the MLO clock signal is represented by tMLO. Rev. A | Page 8 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE