Datasheet AD9670 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Octal Ultrasound AFE With Digital Demodulator |
| Pages / Page | 52 / 10 — AD9670. Data Sheet. tMLO. MLO–. MLO+. HOLD. SETUP. RESET–. RESET+. tHOLD. … |
| Revision | A |
| File Format / Size | PDF / 747 Kb |
| Document Language | English |
AD9670. Data Sheet. tMLO. MLO–. MLO+. HOLD. SETUP. RESET–. RESET+. tHOLD. tSETUP
Model Line for this Datasheet
Text Version of Document
AD9670 Data Sheet tMLO MLO– MLO+ t t HOLD SETUP RESET–
4 00 1- 04
RESET+
1 1 Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode
tMLO MLO– MLO+ tHOLD tSETUP RESET–
5
RESET+
-10 041 1 1 Figure 5. CW Doppler Mode Input MLO±, Pulse Synchronous RESET± Timing, 4LO/8LO/16LO Mode
tMLO MLO– MLO+ tSETUP tHOLD RESET– RESET+
106 41- 10 1 Figure 6. CW Doppler Mode Input MLO±, Pulse Asynchronous RESET± Timing, 4LO/8LO/16LO Mode Rev. A | Page 10 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE
4 00 1- 04
RESET+
1 1 Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode
tMLO MLO– MLO+ tHOLD tSETUP RESET–
5
RESET+
-10 041 1 1 Figure 5. CW Doppler Mode Input MLO±, Pulse Synchronous RESET± Timing, 4LO/8LO/16LO Mode
tMLO MLO– MLO+ tSETUP tHOLD RESET– RESET+
106 41- 10 1 Figure 6. CW Doppler Mode Input MLO±, Pulse Asynchronous RESET± Timing, 4LO/8LO/16LO Mode Rev. A | Page 10 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE
