Datasheet AD8284 (Analog Devices) - 18

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AD8284 Data Sheet SERIAL PORT INTERFACE (SPI)
The AD8284 serial port interface allows the user to configure When W0 and W1 are set to 11, the device enters streaming mode the signal chain for specific functions or operations through a and continues to process data, either reading or writing, structured register space provided inside the chip. The SPI until CS is taken high to end the communication cycle. This offers the user added flexibility and customization depending allows complete memory transfers without the need to provide on the application. Addresses are accessed via the serial port additional instructions. Regardless of the mode, if CS is taken and can be written to or read from via the port. Memory is high in the middle of any byte transfer, the SPI state machine is organized into bytes that can be further divided into fields, as reset and the device waits for a new instruction. documented in the Memory Map section. Detailed operational In addition to the operation modes, the SPI port can be information can be found in the AN-877 Application Note, configured to operate in different manners. For applications Interfacing to High Speed ADCs via SPI. that do not require a control port, the CS line can be tied and Four pins define the serial port interface, or SPI: the SCLK, SDI, held high. This places the remainder of the SPI pins in their SDO, and CS pins. The serial clock pin (SCLK) synchronizes the secondary mode as defined in the AN-877 Application Note, read and write data presented to the device. The serial data Interfacing to High Speed ADCs via SPI. CS can also be tied low input and output pins, SDI and SDO, allow data to be sent to to enable 3-wire mode. When CS is tied low, SCLK, SDO, and and read from the internal memory map registers of the device. SDI are the only pins required for communication. Although The chip select pin (CS) is an active low control that enables or the device is synchronized during power-up, caution must be disables the read and write cycles (see Table 8). exercised when using this mode to ensure that the serial port
Table 8. Serial Port Interface Pins
remains synchronized with the CS line. When operating in
Pin Function
3-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer SCLK Serial clock. The serial shift clock input. SCLK is used to be used exclusively. Without an active CS line, streaming mode synchronize serial interface reads and writes. can be entered but not exited. SDI Serial data input. Data can be sent in MSB-first or LSB-first mode. MSB-first SDO Serial data output. mode is the default at power-up and can be changed by adjusting CS Chip select (active low). This control gates the read and the configuration register. For more information about this and write cycles. other features, see the AN-877 Application Note, Interfacing to The fal ing edge of CS, in conjunction with the rising edge of High Speed ADCs via SPI. SCLK, determines the start of the framing sequence. During an
HARDWARE INTERFACE
instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and The pins described in Table 8 constitute the physical interface Bit Field W1. See Figure 22 and Table 9 for an example of the between the user’s programming device and the serial port of serial timing and its definitions. the AD8284. The SCLK, SDI, and CS pins function as inputs when using the SPI interface. The SDO pin is an output during In normal operation, CS signals to the device that SPI commands readback. are about to be received and processed. When CS is brought low, This interface is flexible enough to be controlled by either serial- the device processes SCLK and SDI to process instructions. programmable read-only memory (PROM) or PIC micro- Normally, CS remains low until the communication cycle is control ers. This provides the user with alternative means, other complete. However, if the AD8284 is connected to a slow than a full SPI control er, for programming the device (see the device, CS can be brought high between bytes, al owing older AN-812 Application Note). microcontrollers enough time to transfer data into the shift registers. CS can be stal ed when transferring one, two, or three bytes of data. Rev. D | Page 18 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products