Datasheet AD9279 (Analog Devices) - 4

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AD9279 Parameter1 T est Conditions/Comments Min Typ Max Unit
Input-Referred Noise Voltage GAIN+ = 1.6 V, RFB = ∞ LNA gain = 15.6 dB 1.12 nV/√Hz LNA gain = 17.9 dB 0.96 nV/√Hz LNA gain = 21.3 dB 0.81 nV/√Hz Noise Figure GAIN+ = 1.6 V, RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 200 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 250 Ω 4.5 dB LNA gain = 21.3 dB, RFB = 350 Ω 3.3 dB Unterminated LNA gain = 15.6 dB, RFB = ∞ 3.5 dB LNA gain = 17.9 dB, RFB = ∞ 2.9 dB LNA gain = 21.3 dB, RFB = ∞ 2.3 dB Correlated Noise Ratio No signal, correlated/uncorrelated −30 dB Output Offset −35 +35 LSB Signal-to-Noise Ratio (SNR) fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V, 67 dBFS fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V 59 dBFS Harmonic Distortion Second Harmonic fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V −72 dBc fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V −72 dBc Third Harmonic fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V −69 dBc fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V −59 dBc Two-Tone Intermodulation (IMD3) fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, −70 dBc ARF1 = 0 dB, ARF2 = −20 dB, GAIN+ = 1.6 VIMD3 relative to ARF2 Channel-to-Channel Crosstalk fIN1 = 5.0 MHz at −1 dBFS −60 dB Overrange condition2 −55 dB Channel-to-Channel Delay Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to 0.3 Degrees Variation 1.6 V GAIN ACCURACY 25°C Gain Law Conformance Error 0 < GAIN+ < 0.16 V 0.5 dB 0.16 V < GAIN+ < 1.44 V −1.6 +1.6 dB 1.44 V < GAIN+ < 1.6 V 0.5 dB Linear Gain Error GAIN+ = 0.8 V, normalized for ideal AAF −1.6 +1.6 dB loss Channel-to-Channel Matching 0.16 V < GAIN+ < 1.44 V 0.1 dB PGA Gain 21/24/27/30 dB GAIN CONTROL INTERFACE Control Range Differential −0.8 +0.8 V Single-ended 0 1.6 V Gain Range GAIN+ = 0 V to 1.6 V 45 dB Scale Factor 28.0 dB/V Response Time 45 dB change 750 ns Gain+ Impedance Single-ended 10 MΩ Gain− Impedance Single-ended 70 kΩ CW DOPPLER MODE LO Frequency fLO = f4LO/4 1 10 MHz Phase Resolution Per channel 22.5 Degrees Output DC Bias (Single-Ended) CWI+, CWI−, CWQ+, CWQ− 1.5 V Output AC Current Range Per CWI+, CWI−, CWQ+, CWQ−, each ±1.25 mA channel enabled Transconductance (Differential) Demodulated IOUT/VIN, per CWI+, CWI−, CWQ+, CWQ− LNA gain = 15.6 dB 1.8 mA/V LNA gain = 17.9 dB 2.4 mA/V LNA gain = 21.3 dB 3.5 mA/V Rev. 0 | Page 4 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE