Datasheet AD9272 (Analog Devices) - 38

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AD9272 SERIAL PORT INTERFACE (SPI)
The AD9272 serial port interface allows the user to configure In addition to the operation modes, the SPI port can be the signal chain for specific functions or operations through a configured to operate in different manners. For applications structured register space provided inside the chip. This offers that do not require a control port, the CSB line can be tied and the user added flexibility and customization, depending on the held high. This places the remainder of the SPI pins in their application. Addresses are accessed via the serial port and can secondary mode as defined in the SDIO Pin and SCLK Pin be written to or read from via the port. Memory is organized sections. CSB can also be tied low to enable 2-wire mode. When into bytes that can be further divided down into fields, as doc- CSB is tied low, SCLK and SDIO are the only pins required for umented in the Memory Map section. Detailed operational communication. Although the device is synchronized during information can be found in the Analog Devices, Inc., AN-877 power-up, caution must be exercised when using this mode to Application Note, Interfacing to High Speed ADCs via SPI. ensure that the serial port remains synchronized with the CSB There are three pins that define the serial port interface or SPI. line. When operating in 2-wire mode, it is recommended to use They are the SCLK, SDIO, and CSB pins. The SCLK (serial a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB clock) is used to synchronize the read and write data presented line, streaming mode can be entered but not exited. to the device. The SDIO (serial data input/output) is a dual- In addition to word length, the instruction phase determines if purpose pin that allows data to be sent to and read from the the serial frame is a read or write operation, allowing the serial internal memory map registers of the device. The CSB (chip port to be used to both program the chip and read the contents select bar) is an active low control that enables or disables the of the on-chip memory. If the instruction is a readback operation, read and write cycles (see Table 15). performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the
Table 15. Serial Port Pins
appropriate point in the serial frame.
Pin Function
Data can be sent in MSB- or LSB-first mode. MSB-first mode SCLK Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. is the default at power-up and can be changed by adjusting the SDIO Serial data input/output. A dual-purpose pin. The typical configuration register. For more information about this and role for this pin is as an input or output, depending on other features, see the AN-877 Application Note, Interfacing to the instruction sent and the relative position in the High Speed ADCs via SPI. timing frame.
HARDWARE INTERFACE
CSB Chip select bar (active low). This control gates the read and write cycles. The pins described in Table 15 constitute the physical interface between the programming device of the user and the serial port The falling edge of the CSB pin in conjunction with the rising edge of the AD9272. The SCLK and CSB pins function as inputs of the SCLK determines the start of the framing sequence. During when using the SPI interface. The SDIO pin is bidirectional, an instruction phase, a 16-bit instruction is transmitted, followed functioning as an input during write phases and as an output by one or more data bytes, which is determined by Bit Field W0 during readback. and Bit Field W1. An example of the serial timing and its In cases where multiple SDIO pins share a common connection, definitions can be found in Figure 69 and Table 16. care should be taken to ensure that proper VOH levels are met. In normal operation, CSB is used to signal to the device that SPI Figure 68 shows the number of SDIO pins that can be connected commands are to be received and processed. When CSB is brought together, assuming the same load as the AD9272 and the low, the device processes SCLK and SDIO to process instructions. resulting VOH level. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instruct- tions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset, and the device waits for a new instruction. Rev. C | Page 38 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE