Datasheet ADRF6516 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 31 MHz, Dual Programmable Filters and Variable Gain Amplifiers |
| Pages / Page | 29 / 9 — Data Sheet. ADRF6516. BANDWIDTH = 31MHz. –40°C, VPS = 3.15V, 3.3V, 3.45V. … |
| Revision | C |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Data Sheet. ADRF6516. BANDWIDTH = 31MHz. –40°C, VPS = 3.15V, 3.3V, 3.45V. DIGITAL GAIN = 111. B (. N (. +25°C,. DIGITAL GAIN = 000
Model Line for this Datasheet
Text Version of Document
Data Sheet ADRF6516 20 40 BANDWIDTH = 31MHz BANDWIDTH = 31MHz 38 15 36 10 34 –40°C, VPS = 3.15V, 3.3V, 3.45V ) 5 DIGITAL GAIN = 111 32 BV B) d d B ( 0 30 N ( 1d AI P G O 28 –5 +25°C, DIGITAL GAIN = 000 VPS = 3.15V, 3.3V, 3.45V 26 –10 +85°C, 24 VPS = 3.15V, 3.3V, 3.45V –15 22 –20
1 1
20 0 5 10 15 20 25 30 35 40
0
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
014
GAIN (dB)
09422-
VGAIN (mV)
09422- Figure 11. Output P1dB vs. Gain at 15 MHz (Bandwidth Setting = 31 MHz) Figure 14. Frequency Response over Supply and Temperature (Bandwidth Setting = 31 MHz, Gain = 30 dB)
40 1000 GAIN = 20dB 35 900 30 800 BW = 1MHz 25 700 s) n ( 20 Y 600 B) A d L 15 N ( 500 DE AI P G 10 400 OU GR 5 300 BW = 10MHz BW = 31MHz 0 200 BW = 5MHz BW = 20MHz –5 100 –10 0 1 10 100
012
0.3 3 30 50
015
FREQUENCY (MHz)
09422-
FREQUENCY (MHz)
09422- Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 15. Group Delay vs. Frequency (Gain = 20 dB) Log Scale
40 2.0 BANDWIDTH = 31MHz 35 1.5 30 s) n 1.0 25 CH ( T A 0.5 20 B) d SM 15 N ( MI 0 Y AI A GAIN = 20dB G L 10 –0.5 DE P 5 OU –1.0 GAIN = 40dB 0 GR –1.5 –5 –10 –2.0 0 10 20 30 40 50 60 70 80 90 100
013
0.3 3 30
016
FREQUENCY (MHz) FREQUENCY (MHz)
09422- 09422- Figure 13. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 16. Group Delay Matching vs. Frequency Linear Scale (Bandwidth Setting = 31 MHz) Rev. C | Page 9 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
1 1
20 0 5 10 15 20 25 30 35 40
0
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
014
GAIN (dB)
09422-
VGAIN (mV)
09422- Figure 11. Output P1dB vs. Gain at 15 MHz (Bandwidth Setting = 31 MHz) Figure 14. Frequency Response over Supply and Temperature (Bandwidth Setting = 31 MHz, Gain = 30 dB)
40 1000 GAIN = 20dB 35 900 30 800 BW = 1MHz 25 700 s) n ( 20 Y 600 B) A d L 15 N ( 500 DE AI P G 10 400 OU GR 5 300 BW = 10MHz BW = 31MHz 0 200 BW = 5MHz BW = 20MHz –5 100 –10 0 1 10 100
012
0.3 3 30 50
015
FREQUENCY (MHz)
09422-
FREQUENCY (MHz)
09422- Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 15. Group Delay vs. Frequency (Gain = 20 dB) Log Scale
40 2.0 BANDWIDTH = 31MHz 35 1.5 30 s) n 1.0 25 CH ( T A 0.5 20 B) d SM 15 N ( MI 0 Y AI A GAIN = 20dB G L 10 –0.5 DE P 5 OU –1.0 GAIN = 40dB 0 GR –1.5 –5 –10 –2.0 0 10 20 30 40 50 60 70 80 90 100
013
0.3 3 30
016
FREQUENCY (MHz) FREQUENCY (MHz)
09422- 09422- Figure 13. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 16. Group Delay Matching vs. Frequency Linear Scale (Bandwidth Setting = 31 MHz) Rev. C | Page 9 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
