Datasheet RX65N, RX651 Groups (Renesas) - 3
| Manufacturer | Renesas |
| Description | 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory |
| Pages / Page | 246 / 3 — Table 1.1. Outline of Specifications (2/10). Classification. … |
| File Format / Size | PDF / 2.8 Mb |
| Document Language | English |
Table 1.1. Outline of Specifications (2/10). Classification. Module/Function. Description
Model Line for this Datasheet
Text Version of Document
RX65N Group, RX651 Group 1. Overview
Table 1.1 Outline of Specifications (2/10) Classification Module/Function Description
Operating modes Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) Boot mode (for the FINE interface) Selection of operating mode by register setting Single-chip mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Endian selectable Clock Clock generation circuit Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator The peripheral module clocks can be set to frequencies above that of the system clock. Main-clock oscillation stoppage detection Separate frequency-division and multiplication settings for the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): Up to 120 MHz Peripheral modules of MTU3, RSPI, SCIi, ETHERC, EDMAC, AES, GLCDC, and DRW2D run in synchronization with PCLKA, which operates at up to 120 MHz. Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): Up to 60 MHz Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a reference clock of the PLL circuit Reset Nine types of reset RES# pin reset: Generated when the RES# pin is driven low. Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 = AVCC1 rises. Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls. Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls. Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls. Deep software standby reset: Generated in response to an interrupt to trigger release from deep software standby. Independent watchdog timer reset: Generated when the independent watchdog timer underflows, or a refresh error occurs. Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error occurs. Software reset: Generated by register setting. Power-on reset If the RES# pin is at the high level when power is supplied, an internal reset is generated. After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified period has elapsed, the reset is cancelled. Voltage detection circuit (LVDA) Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an internal reset or interrupt. Voltage detection circuit 0 Capable of generating an internal reset The option-setting memory can be used to select enabling or disabling of the reset. Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V) Voltage detection circuits 1 and 2 Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V) Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency) Capable of generating an internal reset Two types of timing are selectable for release from reset An internal interrupt can be requested. Detection of voltage rising above and falling below thresholds is selectable. Maskable or non-maskable interrupt is selectable Voltage detection monitoring Event linking R01DS0276EJ0230 Rev.2.30 Page 3 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
Table 1.1 Outline of Specifications (2/10) Classification Module/Function Description
Operating modes Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) Boot mode (for the FINE interface) Selection of operating mode by register setting Single-chip mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Endian selectable Clock Clock generation circuit Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator The peripheral module clocks can be set to frequencies above that of the system clock. Main-clock oscillation stoppage detection Separate frequency-division and multiplication settings for the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): Up to 120 MHz Peripheral modules of MTU3, RSPI, SCIi, ETHERC, EDMAC, AES, GLCDC, and DRW2D run in synchronization with PCLKA, which operates at up to 120 MHz. Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): Up to 60 MHz Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a reference clock of the PLL circuit Reset Nine types of reset RES# pin reset: Generated when the RES# pin is driven low. Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 = AVCC1 rises. Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls. Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls. Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls. Deep software standby reset: Generated in response to an interrupt to trigger release from deep software standby. Independent watchdog timer reset: Generated when the independent watchdog timer underflows, or a refresh error occurs. Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error occurs. Software reset: Generated by register setting. Power-on reset If the RES# pin is at the high level when power is supplied, an internal reset is generated. After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified period has elapsed, the reset is cancelled. Voltage detection circuit (LVDA) Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an internal reset or interrupt. Voltage detection circuit 0 Capable of generating an internal reset The option-setting memory can be used to select enabling or disabling of the reset. Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V) Voltage detection circuits 1 and 2 Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V) Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency) Capable of generating an internal reset Two types of timing are selectable for release from reset An internal interrupt can be requested. Detection of voltage rising above and falling below thresholds is selectable. Maskable or non-maskable interrupt is selectable Voltage detection monitoring Event linking R01DS0276EJ0230 Rev.2.30 Page 3 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
