Datasheet BC3602 (Holtek) - 6
| Manufacturer | Holtek |
| Description | Sub-1GHz Low RX Current FSK/GFSK RF Transceiver |
| Pages / Page | 61 / 6 — BC3602. Symbol. Parameter. Test Conditions. Min. Typ. Max. Unit. LO … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
BC3602. Symbol. Parameter. Test Conditions. Min. Typ. Max. Unit. LO Characteristics. Memory Mapping. Control Register Access
Model Line for this Datasheet
Text Version of Document
BC3602 Symbol Parameter Test Conditions Min. Typ. Max. Unit LO Characteristics
315MHz band 290 — 335 433MHz band 415 — 490 fLO RF Frequency Coverage Range 470~510MHz band 470 — 510 MHz 868MHz band 830 — 1000 915MHz band 870 — 1050 fSTEP LO Frequency Resolution — — — 1 kHz @ 100kHz offset — -90 — 315MHz Phase Noise @ 1MHz offset — -113 — @ 100kHz offset — -89 — 433MHz Phase Noise @ 1MHz offset — -110 — PNLO dBc/Hz @ 100kHz offset — -86 — 868MHz Phase Noise @ 1MHz offset — -109 — @ 100kHz offset — -86 — 915MHz Phase Noise @ 1MHz offset — -109 — Crystal Oscillator fXTAL X’tal Frequency — — 16 — MHz ESR X’tal Equivalent Series Resistance — — — 100 Ω CLOAD X’tal Capacitor Load — 12 16 20 pF TOL X’tal Tolerance — -20 — +20 dBc/Hz tSU X’tal Startup Time 49US XO — — 1 ms
Memory Mapping
00h Common Area 1Fh 20h Bank 0 Bank 1 Bank 2 3Fh Common Area: It contains 32 bytes space. Accessing addresses 00h~1Fh always means to access the Common Area regardless of Bank Pointer configuration. Bank 0~2: Each bank contains 32 bytes space. They are selected by the Bank Pointer. The Bank Pointer, BANK[1:0], which is defined in the Common Area, can be set directly by the Set Register Bank command and read/written by the Control Register command.
Control Register Access
Read/Write Register CMD reg DATA reg DATA reg+1 DATA reg+2 DATA reg+3 DATA reg+4 Read/Write RF FIFO CMD FIFO DATA0 DATA1 DATA2 DATA3 DATA4 DATAn Read/Write CMD DATA0 DATA1 DATA2 DATA3 SYNCWORD register SYNCWORD
Strobe Command Followed by n-byte Data (CmdD)
Rev. 1.00 6 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
315MHz band 290 — 335 433MHz band 415 — 490 fLO RF Frequency Coverage Range 470~510MHz band 470 — 510 MHz 868MHz band 830 — 1000 915MHz band 870 — 1050 fSTEP LO Frequency Resolution — — — 1 kHz @ 100kHz offset — -90 — 315MHz Phase Noise @ 1MHz offset — -113 — @ 100kHz offset — -89 — 433MHz Phase Noise @ 1MHz offset — -110 — PNLO dBc/Hz @ 100kHz offset — -86 — 868MHz Phase Noise @ 1MHz offset — -109 — @ 100kHz offset — -86 — 915MHz Phase Noise @ 1MHz offset — -109 — Crystal Oscillator fXTAL X’tal Frequency — — 16 — MHz ESR X’tal Equivalent Series Resistance — — — 100 Ω CLOAD X’tal Capacitor Load — 12 16 20 pF TOL X’tal Tolerance — -20 — +20 dBc/Hz tSU X’tal Startup Time 49US XO — — 1 ms
Memory Mapping
00h Common Area 1Fh 20h Bank 0 Bank 1 Bank 2 3Fh Common Area: It contains 32 bytes space. Accessing addresses 00h~1Fh always means to access the Common Area regardless of Bank Pointer configuration. Bank 0~2: Each bank contains 32 bytes space. They are selected by the Bank Pointer. The Bank Pointer, BANK[1:0], which is defined in the Common Area, can be set directly by the Set Register Bank command and read/written by the Control Register command.
Control Register Access
Read/Write Register CMD reg DATA reg DATA reg+1 DATA reg+2 DATA reg+3 DATA reg+4 Read/Write RF FIFO CMD FIFO DATA0 DATA1 DATA2 DATA3 DATA4 DATAn Read/Write CMD DATA0 DATA1 DATA2 DATA3 SYNCWORD register SYNCWORD
Strobe Command Followed by n-byte Data (CmdD)
Rev. 1.00 6 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
