Datasheet BC3602 (Holtek) - 9
| Manufacturer | Holtek |
| Description | Sub-1GHz Low RX Current FSK/GFSK RF Transceiver |
| Pages / Page | 61 / 9 — BC3602. • RC1: Reset/Clock Control Register 1. Bit. PWRON. FSYCK_RDY. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
BC3602. • RC1: Reset/Clock Control Register 1. Bit. PWRON. FSYCK_RDY. XCLK_RDY. XCLK_EN. FSYCK_DIV[1:0]. FSYCK_EN. RST_LL
Model Line for this Datasheet
Text Version of Document
BC3602 • RC1: Reset/Clock Control Register 1 Bit 7 6 5 4 3 2 1 0
Name PWRON FSYCK_RDY XCLK_RDY XCLK_EN FSYCK_DIV[1:0] FSYCK_EN RST_LL R/W R/W R R R/W R/W R/W R/W POR 1 — — — 0 0 0 — Reset — 0 0 1 — — — 0 Bit 7
PWRON
: 3.3V power on flag This bit is only set to 1 by power on reset and not affected by software reset of strobe command. After being set high, this bit should be cleared by application program. The firmware can check this flag status and determine whether to execute auto calibration in the Light Sleep mode. Bit 6
FSYCK_RDY
: FSYCK clock ready flag (ready only) 0: Not ready 1: Ready This bit is used to indicate that whether the FSYCK clock is ready for operation. This bit will be automatically cleared when FSYCK_EN=0, when power on reset occurs or when a Deep Sleep command or an Idle command is received. Bit 5
XCLK_RDY
: XCLK clock ready flag (ready only) 0: Not ready 1: Ready This bit is used to indicate whether the XCLK debounce counter is full and XCLK is ready for operation. Note that when exiting the Deep Sleep state, this flag may need a certain period before being set high. This bit will be automatically cleared to zero when XCLK_EN=0, when RST_LL=1, when power on reset occurs or when a software reset command, a Deep Sleep command or an Idle command is received. Bit 4
XCLK_EN
: XCLK clock enable 0: Disable 1: Enable Setting this bit high will enable the XCLK path to the baseband block while clearing this bit to zero can save power if required. The XCLK clock should be enabled when writing data to the FIFO. Bit 3~2
FSYCK_DIV[1:0]
: FSYCK clock (XCLK division) selection 00: 1/1 XCLK 01: 1/2 XCLK 10: 1/4 XCLK 11: 1/8 XCLK Bit 1
FSYCK_EN
: FSYCK clock enable 0: Disable 1: Enable Bit 0
RST_LL
: Low voltage (1.2V) logic reset control 0: Release reset 1: Reset Rev. 1.00 9 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
Name PWRON FSYCK_RDY XCLK_RDY XCLK_EN FSYCK_DIV[1:0] FSYCK_EN RST_LL R/W R/W R R R/W R/W R/W R/W POR 1 — — — 0 0 0 — Reset — 0 0 1 — — — 0 Bit 7
PWRON
: 3.3V power on flag This bit is only set to 1 by power on reset and not affected by software reset of strobe command. After being set high, this bit should be cleared by application program. The firmware can check this flag status and determine whether to execute auto calibration in the Light Sleep mode. Bit 6
FSYCK_RDY
: FSYCK clock ready flag (ready only) 0: Not ready 1: Ready This bit is used to indicate that whether the FSYCK clock is ready for operation. This bit will be automatically cleared when FSYCK_EN=0, when power on reset occurs or when a Deep Sleep command or an Idle command is received. Bit 5
XCLK_RDY
: XCLK clock ready flag (ready only) 0: Not ready 1: Ready This bit is used to indicate whether the XCLK debounce counter is full and XCLK is ready for operation. Note that when exiting the Deep Sleep state, this flag may need a certain period before being set high. This bit will be automatically cleared to zero when XCLK_EN=0, when RST_LL=1, when power on reset occurs or when a software reset command, a Deep Sleep command or an Idle command is received. Bit 4
XCLK_EN
: XCLK clock enable 0: Disable 1: Enable Setting this bit high will enable the XCLK path to the baseband block while clearing this bit to zero can save power if required. The XCLK clock should be enabled when writing data to the FIFO. Bit 3~2
FSYCK_DIV[1:0]
: FSYCK clock (XCLK division) selection 00: 1/1 XCLK 01: 1/2 XCLK 10: 1/4 XCLK 11: 1/8 XCLK Bit 1
FSYCK_EN
: FSYCK clock enable 0: Disable 1: Enable Bit 0
RST_LL
: Low voltage (1.2V) logic reset control 0: Release reset 1: Reset Rev. 1.00 9 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
