Datasheet HT68F001, HT68F0012 (Holtek) - 6

HT68F001/HT68F0012 HT68F001/HT68F0012 Cost-Effective Flash MCU Cost-Effective Flash MCU Selection Table
The devices in this series offer similar functions differing only in the main system clock. The following table summarizes the main features of each device.
Part No. System Data Clock VDD Program Memory Memory I/O Timer/Event Counter Stacks Time Base Package
HT6�F001 32kHz 1.�V-5.5V 512×12 16×� 6 1 2 1 �SOP HT6�F0012 512kHz
Block Diagram
ROM RAM 0.5K×12 16×8 Watchdog Stack Timer 2-Level HT8 MCU Core Timer Pin-Shared Port A SYSCLK Function Driver PA0~PA5 R I/O SF LIRC Digital 32kHz Peripherals /16 VDD VDD VSS VSS IRC Time Base 512kHz Clock System : Pin-Shared Node : The LIRC is only for the HT68F001, and the IRC is only for the HT68F0012
Pin Assignment
PA0/ICPDA 1 8 PA5 VSS 2 7 PA4 VDD 3 6 PA3/TC PA1 4 5 PA2/ICPCK
HT68F001/HT68F0012 8 SOP-A
PA0/ICPDA 1 16 PA5 VSS 2 15 PA4 VDD 3 14 PA3/TC PA1 4 13 PA2/ICPCK NC 5 12 NC NC 6 11 NC NC 7 10 NC OCDSCK 8 9 OCDSDA
HT68V001/HT68V0012 16 NSOP-A
Note: The OCDSDA and OCDSCK pins are used as the OCDS dedicated pins and only available for the HT68V001/0012 device which is the OCDS EV chip of the HT68F001/0012. Rev. 1.20 6 ���i� 1�� 201� Rev. 1.20 � ���i� 1�� 201� Document Outline Features CPU Features Peripheral Features General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics Low Speed Internal Oscillator Characteristics (LIRC) – HT68F001 Low Speed Internal Oscillator Characteristics (IRC) – HT68F0012 System Start Up Time Characteristics Input/Output Characteristics Power on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0 Memory Pointers – MP0 Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP Status Register – STATUS Oscillators Oscillator Overview System Clock Configurations Internal 32kHz Oscillator – LIRC Internal 512kHz Oscillator – IRC Operating Modes and System Clocks System Clocks System Operation Modes Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors Port A Wake-up I/O Port Control Registers I/O Pin Structures Programming Considerations Timer/Event Counter Timer/Event Counter Registers – TMR, TMRC Timer Mode Event Counter Mode Pulse Width Capture Mode Interrupts Interrupt Registers Interrupt Operation Time Base Interrupt Interrupt Wake-up Function Programming Considerations Application Circuits Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 8-pin SOP (150mil) Outline Dimensions