Datasheet ADP5073 (Analog Devices) - 10

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ADP5073 Data Sheet THEORY OF OPERATION VIN CIN CVREG SYNC/ FREQ AVIN VREG PVIN HIGH VOLTAGE CURRENT REGULATOR SENSE INVERTER HIGH VOLTAGE D1 PWM CONTROL SW EN BAND GAP SLEW L1 COUT PLL SLEW ERROR AMP RFT REF OSCILLATOR FB VREG EN CONTROL RFB VREF REF_1.6V RPG THERMAL VREG REF FB (OPTIONAL) SHUTDOWN PWRGD COMP 4µA CVREF UVLO POWER START-UP REFERENCE REF GOOD RC TIMERS GENERATOR OVP REF_1.6V C SS GND C R
023
SS (OPTIONAL)
12817- Figure 21. Functional Block Diagram
PWM MODE OSCILLATOR AND SYNCHRONIZATION
The inverting regulator in the ADP5073 operates at a fixed fre- A phase-locked loop (PLL)-based oscil ator generates the internal quency set by an internal oscil ator. At the start of each oscil ator clock and offers a choice of two internal y generated frequency cycle, the MOSFET switch turns on, applying a positive voltage options or external clock synchronization. The switching frequency across the inductor. The inductor current (IINDUCTOR) increases is configured using the SYNC/FREQ pin options shown in Table 6. until the current sense signal crosses the peak inductor current For external synchronization, connect the SYNC/FREQ pin to a threshold that turns off the MOSFET switch; this threshold is set suitable clock source. The PLL locks to an input clock within by the error amplifier output. During the MOSFET off time, the the range specified by fSYNC. inductor current declines through the external diode until the next oscillator clock pulse starts a new cycle. The ADP5073 regulates the
Table 6. SYNC/FREQ Pin Options
output voltage by adjusting the peak inductor current threshold.
SYNC/FREQ Pin Switching Frequency SKIP MODE
High 2.4 MHz Low 1.2 MHz During light load operation, the regulator can skip pulses to External Clock 1× clock frequency maintain output voltage regulation. Skipping pulses increases the device efficiency. The COMP voltage is monitored internal y
INTERNAL REGULATORS
and when it fal s below a threshold (due to the output voltage rising above the target during a switching cycle), the next switching The internal VREG regulator in the ADP5073 provides a stable cycle is skipped. This voltage is monitored on a cycle-by-cycle power supply for the internal circuitry. The VREG supply provides basis. During skip operation, the output ripple is increased and a high signal for device configuration pins but must not be used the ripple frequency varies. The choice of inductor defines the to supply external circuitry. output current below which skip mode occurs. The VREF regulator provides a reference voltage for the inverting
UNDERVOLTAGE LOCKOUT (UVLO)
regulator feedback network to ensure a positive feedback voltage on the FB pin. A current-limit circuit is included for both internal The UVLO circuitry monitors the AVIN pin voltage level. If the regulators to protect the circuit from accidental loading. input voltage drops below the VUVLO_FALLING threshold, the regulator turns off. After the AVIN pin voltage rises above the VUVLO_RISING threshold, the soft start period initiates, and the regulator is enabled. Rev. A | Page 10 of 17 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE SKIP MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATORS PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION POWER GOOD THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection Loop Compensation COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE