Datasheet ADN2892 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 3.3 V 4.25 Gb/s Limiting Amplifier |
| Pages / Page | 16 / 10 — ADN2892. Data Sheet. THEORY OF OPERATION LIMITING AMPLIFIER. RECEIVED … |
| Revision | C |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
ADN2892. Data Sheet. THEORY OF OPERATION LIMITING AMPLIFIER. RECEIVED SIGNAL STRENGTH INDICATOR (RSSI). Input Buffer
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ADN2892 Data Sheet THEORY OF OPERATION LIMITING AMPLIFIER RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) Input Buffer
The ADN2892 has an on-chip, RSSI circuit. By monitoring the The ADN2892 limiting amplifier provides differential inputs current supplied to the photodiode, the RSSI circuit provides an (PIN/NIN), each with a single-ended, on-chip 50 Ω termination. accurate, average power measurement. The output of the RSSI is a The amplifier can accept either dc-coupled or ac-coupled signals; current that is directly proportional to the average amount of PIN however, an ac-coupled signal is recommended. Using a dc- photodiode current. Placing a resistor between the RSSI_OUT pin coupled signal, the amplifier needs a nominal VCC − 0.7 V and GND converts the current to a GND referenced voltage. This common-mode voltage and ±0.5 V headroom. If the input function eliminates the need for external RSSI circuitry for SFF- common-mode voltage is 2.4 V, the available headroom is reduced 8472-compliant optical receivers. For more information, see down to ±0.3 V. Figure 12 to Figure 16. The ADN2892 limiting amplifier is a high gain device. It is Connect the PD_VCC, PD_CATHODE, and RSSI_OUT pins to susceptible to dc offsets in the signal path. The pulse width AVCC to disable the RSSI feature. distortion presented in the NRZ data or a distortion generated by
SQUELCH MODE
the TIA may appear as dc offset or a corrupted signal to the ADN2892 inputs. An internal offset correction loop can Driving the SQUELCH input to logic high disables the limiting compensate for certain levels of offset. amplifier outputs. Using LOS output to drive the SQUELCH input, the limiting amplifier outputs stop toggling anytime a
CML Output Buffer
signal input level to the limiting amplifier drops below the The ADN2892 provides differential CML outputs, OUTP and programmed LOS threshold. OUTN. Each output has an internal 50 Ω termination to VCC. The SQUELCH pin has a 100 kΩ, internal pul -down resistor.
LOSS-OF-SIGNAL (LOS) DETECTOR BW_SEL (BANDWIDTH SELECTION) MODE
The on-chip LOS circuit drives LOS to logic high when the Driving the BW_SEL input signal to logic high, the amplifier input signal level falls below a user-programmable threshold. provides a 3.8 GHz bandwidth. Driving the BW_SEL input The threshold level can be set anywhere from 3.5 mV p-p to signal to logic low, the amplifier accepts input signals through a 35 mV p-p typical by a resistor connected between the 1.5 GHz, 2-pole, low-pass filter that improves receiving THRADJ pin and VEE. See Figure 6 and Figure 7 for the LOS sensitivity. threshold vs. THRADJ. The ADN2892 LOS circuit has an electrical hysteresis greater than 2.5 dB to prevent chatter at the The low-pass filter reduces the possible relaxation oscillation of LOS signal. The LOS output is an open-col ector output that low speed, low cost laser source by limiting the input signal must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor. bandwidth. The BW_SEL pin has a 100 kΩ, on-chip pul -up resistor. Setting the BW_SEL pin open disables the low-pass filter.
LOS_INV (LOSE OF SIGNAL_INVERT) MODE
Some applications, such as SFF, need the LOS assertion and deassertion voltage reversed. When the LOS_INV pin is pul ed to logic high, the LOS output assertion is pulled down to electrical low. The LOS_INV pin has a 100 kΩ on-chip, pul -down resistor. Rev. C | Page 10 of 16 Document Outline Features Applications General Description Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Limiting Amplifier Input Buffer CML Output Buffer Loss-of-Signal (LOS) Detector Received Signal Strength Indicator (RSSI) Squelch Mode BW_SEL (Bandwidth Selection) Mode LOS_INV (Lose of Signal_Invert) Mode Applications Information PCB Design Guidelines Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP Pad Coating and Pb-Free Soldering Outline Dimensions Ordering Guide
ADN2892 Data Sheet THEORY OF OPERATION LIMITING AMPLIFIER RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) Input Buffer
The ADN2892 has an on-chip, RSSI circuit. By monitoring the The ADN2892 limiting amplifier provides differential inputs current supplied to the photodiode, the RSSI circuit provides an (PIN/NIN), each with a single-ended, on-chip 50 Ω termination. accurate, average power measurement. The output of the RSSI is a The amplifier can accept either dc-coupled or ac-coupled signals; current that is directly proportional to the average amount of PIN however, an ac-coupled signal is recommended. Using a dc- photodiode current. Placing a resistor between the RSSI_OUT pin coupled signal, the amplifier needs a nominal VCC − 0.7 V and GND converts the current to a GND referenced voltage. This common-mode voltage and ±0.5 V headroom. If the input function eliminates the need for external RSSI circuitry for SFF- common-mode voltage is 2.4 V, the available headroom is reduced 8472-compliant optical receivers. For more information, see down to ±0.3 V. Figure 12 to Figure 16. The ADN2892 limiting amplifier is a high gain device. It is Connect the PD_VCC, PD_CATHODE, and RSSI_OUT pins to susceptible to dc offsets in the signal path. The pulse width AVCC to disable the RSSI feature. distortion presented in the NRZ data or a distortion generated by
SQUELCH MODE
the TIA may appear as dc offset or a corrupted signal to the ADN2892 inputs. An internal offset correction loop can Driving the SQUELCH input to logic high disables the limiting compensate for certain levels of offset. amplifier outputs. Using LOS output to drive the SQUELCH input, the limiting amplifier outputs stop toggling anytime a
CML Output Buffer
signal input level to the limiting amplifier drops below the The ADN2892 provides differential CML outputs, OUTP and programmed LOS threshold. OUTN. Each output has an internal 50 Ω termination to VCC. The SQUELCH pin has a 100 kΩ, internal pul -down resistor.
LOSS-OF-SIGNAL (LOS) DETECTOR BW_SEL (BANDWIDTH SELECTION) MODE
The on-chip LOS circuit drives LOS to logic high when the Driving the BW_SEL input signal to logic high, the amplifier input signal level falls below a user-programmable threshold. provides a 3.8 GHz bandwidth. Driving the BW_SEL input The threshold level can be set anywhere from 3.5 mV p-p to signal to logic low, the amplifier accepts input signals through a 35 mV p-p typical by a resistor connected between the 1.5 GHz, 2-pole, low-pass filter that improves receiving THRADJ pin and VEE. See Figure 6 and Figure 7 for the LOS sensitivity. threshold vs. THRADJ. The ADN2892 LOS circuit has an electrical hysteresis greater than 2.5 dB to prevent chatter at the The low-pass filter reduces the possible relaxation oscillation of LOS signal. The LOS output is an open-col ector output that low speed, low cost laser source by limiting the input signal must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor. bandwidth. The BW_SEL pin has a 100 kΩ, on-chip pul -up resistor. Setting the BW_SEL pin open disables the low-pass filter.
LOS_INV (LOSE OF SIGNAL_INVERT) MODE
Some applications, such as SFF, need the LOS assertion and deassertion voltage reversed. When the LOS_INV pin is pul ed to logic high, the LOS output assertion is pulled down to electrical low. The LOS_INV pin has a 100 kΩ on-chip, pul -down resistor. Rev. C | Page 10 of 16 Document Outline Features Applications General Description Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Limiting Amplifier Input Buffer CML Output Buffer Loss-of-Signal (LOS) Detector Received Signal Strength Indicator (RSSI) Squelch Mode BW_SEL (Bandwidth Selection) Mode LOS_INV (Lose of Signal_Invert) Mode Applications Information PCB Design Guidelines Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP Pad Coating and Pb-Free Soldering Outline Dimensions Ordering Guide
