Datasheet ADL5306 (Analog Devices) - 10

ManufacturerAnalog Devices
Description60 dB-RANGE (100 nA-100 µA) Low-Cost Logarithmic Converter
Pages / Page16 / 10 — MANAGING INTERCEPT AND SLOPE. RESPONSE TIME AND NOISE CONSIDERATIONS
File Format / SizePDF / 2.2 Mb
Document LanguageEnglish

MANAGING INTERCEPT AND SLOPE. RESPONSE TIME AND NOISE CONSIDERATIONS

MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS

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ADL5306 It is apparent that this output should be zero for IPD = IREF, and
MANAGING INTERCEPT AND SLOPE
would need to swing negative for smaller values of input As previously noted, the internally generated 2.5 V bias current. To avoid this, IREF would need to be as small as the combines with the on-chip resistors to introduce an accurate smallest value of IPD. In the ADL5306, an internal offset voltage offset voltage of 0.8 V at the VLOG pin, equivalent to four is added to VLOG to shift it upward by 0.8 V. This moves the decades. This results in a logarithmic transfer function that can intercept to the left by four decades, from 10 µA to 1 nA: be written as ILOG = IY log10(IPD / IINTC) (4) VLOG = VY log10 (104 × IPD / IREF)= VY log10 (IPD / IINTC) (6) where IINTC is the operational / value of the intercept current. where IINTC = IREF /104 Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this Thus, the effective intercept current, IINTC, is only one ten- situation (discussed later). thousandth of IREF, corresponding to 10 nA when using the recommended value of I The voltage V REF = 100 µA. LOG is generated by applying ILOG to an internal resistance of 4.55 kΩ, formed by the parallel combination of a The slope can be reduced by attaching a resistor to the VLOG 6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the pin. This is strongly discouraged because the on-chip resistors internal 2.5 V reference. At the VLOG pin, the output current will not ratio correctly to the added resistance. Also, it is rare ILOG generates a voltage of that one would wish to lower the basic slope of 10 mV/dB; if this is necessary, it should be done at the low impedance output VLOG = ILOG × 4.55 kΩ of the buffer, which is provided to avoid such miscalibration = 44 µA × 4.55 kΩ × log and allow higher slopes to be used. 10 (IPD / IREF) (5) The ADL5306 buffer is essentially an uncommitted op amp = VY log10 (IPD / IREF) with rail-to-rail output swing, good load driving capabilities, where V and a unity-gain bandwidth of >20 MHz. In addition to Y = 200 mV/decade or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and will result allowing the introduction of gain using standard feedback in an overall scaling uncertainty due to the variability of the on- networks, thereby increasing the slope voltage, VY, the buffer chip resistors. Consequently, this practice is not recommended. can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. For more details, see VLOG may also swing below ground when dual supplies (VP and the AD8304 Data Sheet. VN) are used. When VN = -0.5 V or more negative, the input pins INPT and IREF may be positioned at ground level simply
RESPONSE TIME AND NOISE CONSIDERATIONS
by grounding VSUM. The response time and output noise of the ADL5306 are fundamentally a function of the signal current IPD. For small currents, the bandwidth is proportional to IPD. The output’s low frequency voltage-noise spectral density is a function of IPD, and increases for small values of IREF. For details of noise and bandwidth performance of translinear log amps, see the AD8304 Data Sheet. Rev. 0 | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL STRUCTURE THEORY MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS APPLICATIONS USING A NEGATIVE SUPPLY CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE