Datasheet P9222-R (IDT) - 5

ManufacturerIDT
DescriptionWireless Power Receiver for Low Power Applications
Pages / Page52 / 5 — P9222-R Datasheet. Figure 10. Active Charging Area (Efficiency, 14 × 15 …
Revision20190927
File Format / SizePDF / 2.8 Mb
Document LanguageEnglish

P9222-R Datasheet. Figure 10. Active Charging Area (Efficiency, 14 × 15 mm) .18

P9222-R Datasheet Figure 10 Active Charging Area (Efficiency, 14 × 15 mm) .18

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P9222-R Datasheet
Figure 10. Active Charging Area (Efficiency, 14 × 15 mm) .18
Figure 11. Load Transient Response 1 (Vout = 5V, Iout 0mA to 500mA).18
Figure 12. Load Transient Response 2 (Vout = 5V, Iout 0mA to 1000mA).18
Figure 13. Ping Detect Timing .18
Figure 14. AC Modulation (COM1) .18
Figure 15. RTH1 and R21 Schematic Location .21
Figure 16. RTH1 and R21 PCB Location.21
Figure 17. Rx Modulation Components .23
Figure 18. Communication Packet Structure .24
Figure 19. WPC Packet Example with Reference Clock Shown .24
Figure 20. Byte Encoding Scheme .24
Figure 21. WPC System Feedback Control BPP Mode .25
Figure 22. Dual Resonant Circuits with Receiver Coil .27
Figure 23. P9222-R Recommended Enable Default State Configurations .28
Figure 24. GP0 Pin External Connection to Thermistor Configuration .29
Figure 25. GP2 Pin External Connections for External EEPROM Selection .30
Figure 26. Ping Detection – Typical Application Schematic Components and Connections .30
Figure 27. P9222-R Ping Detect Waveforms .31
Figure 28. Writing to the Vout_Set Register using P9222-R Windows GUI.33
Figure 29. Changing the Default VOUT Value using the P9222-R Windows GUI .34
Figure 30. Changing the Default FOD Registers using the P9222-R Windows GUI .36
Figure 31. Modulation and INT Settings Tab .37
Figure 32. Applications Schematic .48 List of Tables
Table 1. Pin Descriptions.8 Table 2. Absolute Maximum Ratings .10 Table 3. Thermal Characteristics for 40-WLCSP Package .11 Table 4. ESD Information .11 Table 5. Electrical Characteristics .12 Table 6. Recommended Coil Manufacturer .27 Table 7. Recommended RC Values for PDET_RC Components Based on Capacitance and Ping Interval .31 Table 8. Recommended Maximum Estimated Power Loss .35 Table 9. Chip Part Number ID Register, Chip_ID_L (0x00), Chip_ID_H (0x01) .38 Table 10. Chip Revision Register, Chip_Rev (0x02) .38
Table 11. OTP Firmware Revision Registers, OTP_FW_Major (0x04), OTP_FW_Minor (0x06) .38
Table 12. Status Registers, Status_L (0x34), Status_H (0x35) .39
Table 13. Interrupt Registers, INT_L (0x36), INT_H (0x37)[a] .39
Table 14. Interrupt Enable Registers, INT_Enable_L (0x38), INT_Enable_H (0x39) .40 © 2019 Integrated Device Technology, Inc. 5 September 27, 2019