Datasheet CD4538BC (Fairchild) - 3

CD453 Theory of Operation 8BC FIGURE 2. Trigger Operation Retrigger Operation
The block diagram of the CD4538BC is shown in Figure 1, The CD4538BC is retriggered if a valid trigger occurs(3) fol- with circuit operation following. lowed by another valid trigger(4) before the Q output has As shown in Figure 1 and Figure 2, before an input trigger returned to the quiescent (zero) state. Any retrigger, after occurs, the monostable is in the quiescent state with the Q the timing node voltage at pin 2 or 14 has begun to rise output low, and the timing capacitor CX completely charged from VREF1, but has not yet reached VREF2, will cause an to VDD. When the trigger input A goes from VSS to VDD increase in output pulse width T. When a valid retrigger is (while inputs B and CD are held to VDD) a valid trigger is initiated(4), the voltage at T2 will again drop to VREF1 before recognized, which turns on comparator C1 and N-Channel progressing along the RC charging curve toward VDD. The transistor N1(1). At the same time the output latch is set. Q output will remain high until time T, after the last valid With transistor N1 on, the capacitor CX rapidly discharges retrigger. toward VSS until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off.
Reset Operation
Comparator C1 then turns off while at the same time com- The CD4538BC may be reset during the generation of the parator C2 turns on. With transistor N1 off, the capacitor CX output pulse. In the reset mode of operation, an input pulse begins to charge through the timing resistor, RX, toward on CD sets the reset latch and causes the capacitor to be VDD. When the voltage across CX equals VREF2, compara- fast charged to V tor C2 changes state causing the output latch to reset (Q DD by turning on transistor Q1(5). When the voltage on the capacitor reaches V goes low) while at the same time disabling comparator C2. REF2, the reset latch This ends the timing cycle with the monostable in the qui- will clear and then be ready to accept another pulse. If the escent state, waiting for the next trigger. CD input is held low, any trigger inputs that occur will be A valid trigger is also recognized when trigger input B goes inhibited and the Q and Q outputs of the output latch will from V not change. Since the Q output is reset when an input low DD to VSS (while input A is at VSS and input CD is at level is detected on the CD input, the output pulse T can be VDD)(2). made significantly shorter than the minimum pulse width It should be noted that in the quiescent state CX is fully specification. charged to VDD, causing the current through resistor RX to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the CD4538BC is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input wave- form. 3 www.fairchildsemi.com