Datasheet T5808 (TDK) - 9
| Manufacturer | TDK |
| Description | Bottom-Port SoundWire Digital Multi-Mode Microphone |
| Pages / Page | 41 / 9 — T5808. TABLE 12. DIGITAL INPUT/OUTPUT CHARACTERISTICS. PARAMETER. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
T5808. TABLE 12. DIGITAL INPUT/OUTPUT CHARACTERISTICS. PARAMETER. CONDITIONS. MIN. TYP. MAX. UNITS. NOTES
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T5808 TABLE 12. DIGITAL INPUT/OUTPUT CHARACTERISTICS
TA = 25°C, 1.62V < VDD < 1.98V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
Input Voltage High (VIH) 0.65 × VDD V Input Voltage Low (VIL) 0.35 × VDD V Output Voltage High (VOH) ILOAD = 0.5 mA 0.7 × VDD VDD V Output Voltage Low (VOL) ILOAD = 0.5 mA 0 0.3 × VDD V
TABLE 13. DIGITAL (PHY) INPUT/OUTPUT TIMING CHARACTERISTICS
TA = 25°C, 1.7V < VDD < 1.9V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
fSWCLK Input clock frequency 0.024 12.288 MHz tCLKIN (t_1/f_Clock) Input clock period 81 41,666 ns t_Slew_Clock Clock Slew Time 2 5.4 ns Clock Duty Cycle fSWCLK < 12.288MHz 45 50 55 % t_ISetup_min_Data Data input setup time 0 ns 7 t_IHold_min_Data Data input hold time 4 ns 7 t_ZD_Data_Min Data output enable time from initial clock edge 7.9 ns t_DZ_Data_Max Data output disable time from subsequent clock edge 4 ns t_OV_Data_Max Data output valid time 27.9 ns
Note 7:
Guaranteed by design
Figure 2.
Digital Timing – Clock Output Page 9 of 41 Document Number: DS-000269 Revision: 1.1
TA = 25°C, 1.62V < VDD < 1.98V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
Input Voltage High (VIH) 0.65 × VDD V Input Voltage Low (VIL) 0.35 × VDD V Output Voltage High (VOH) ILOAD = 0.5 mA 0.7 × VDD VDD V Output Voltage Low (VOL) ILOAD = 0.5 mA 0 0.3 × VDD V
TABLE 13. DIGITAL (PHY) INPUT/OUTPUT TIMING CHARACTERISTICS
TA = 25°C, 1.7V < VDD < 1.9V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
fSWCLK Input clock frequency 0.024 12.288 MHz tCLKIN (t_1/f_Clock) Input clock period 81 41,666 ns t_Slew_Clock Clock Slew Time 2 5.4 ns Clock Duty Cycle fSWCLK < 12.288MHz 45 50 55 % t_ISetup_min_Data Data input setup time 0 ns 7 t_IHold_min_Data Data input hold time 4 ns 7 t_ZD_Data_Min Data output enable time from initial clock edge 7.9 ns t_DZ_Data_Max Data output disable time from subsequent clock edge 4 ns t_OV_Data_Max Data output valid time 27.9 ns
Note 7:
Guaranteed by design
Figure 2.
Digital Timing – Clock Output Page 9 of 41 Document Number: DS-000269 Revision: 1.1
