Datasheet MTD1N60E (Motorola)

ManufacturerMotorola
DescriptionTMOS E−FET Power Field Effect Transistor DPAK for Surface Mount. N−Channel Enhancement−Mode Silicon Gate
Pages / Page10 / 1 — Order this document. SEMICONDUCTOR TECHNICAL DATA. by MTD1N60E/D. …
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Order this document. SEMICONDUCTOR TECHNICAL DATA. by MTD1N60E/D. Motorola Preferred Device. TMOS POWER FET

Datasheet MTD1N60E Motorola, Revision: XXX

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MOTOROLA
Order this document SEMICONDUCTOR TECHNICAL DATA by MTD1N60E/D
Designer’s Data Sheet MTD1N60E TMOS E−FET.
Motorola Preferred Device
Power Field Effect Transistor DPAK for Surface Mount
TMOS POWER FET N−Channel Enhancement−Mode Silicon Gate 1.0 AMPERE 600 VOLTS
This high voltage MOSFET uses an advanced termination
RDS(on) = 8.0 OHM
scheme to provide enhanced voltage−blocking capability without degrading performance over time. In addition this advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a  drain−to−source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating D safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified G
CASE 369A−13, Style 2
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
DPAK
Fast Recovery Diode S • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Surface Mount Package Available in 16 mm, 13−inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−Source Voltage VDSS 600 Vdc Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 600 Vdc Gate−Source Voltage — Continuous VGS ± 20 Vdc — Non−Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk Drain Current — Continuous ID 1.0 Adc — Continuous @ 100°C ID 0.8 — Single Pulse (tp ≤ 10 µs) IDM 3.0 Apk Total Power Dissipation PD 40 Watts Derate above 25°C 0.32 W/°C Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size 1.75 Watts Operating and Storage Temperature Range TJ, Tstg − 55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C EAS 45 mJ (VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance — Junction to Case RθJC 3.13 °C/W — Junction to Ambient RθJA 100 — Junction to Ambient, when mounted to minimum recommended pad size RθJA 71.4 Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV XXX
Motorola TMOS Power MOSFET Transistor Device Data 1 Motorola, Inc. 1995