Data Brief SZ1105 (Silanna) - 2

PRODUCT BRIEF SZ1105 Pinout CLAMP 1 16 CLMP_S 15 VBULK_S SW 3 14 VAUX_S BOOT_CL 4 13 V5OUT 12 FB GND 6 11 ISNS V10 7 10 DGND GATE 8 9 TEMP Figure 3. SZ1105, SOIC16-2L, 1.27 mm Pitch Package Pinout – Device Top View Pin Descriptions Voltage Category Pin # Name Description (Vdc)
Drain of Active Clamp (ACL) FET. Connect through a clamp capacitor to 1 CLAMP UHV (620 V) VBULK Switching node. Connect to transformer primary and Drain of the Primary N- 3 SW UHV (620 V) FET Bootstrap supply input for internal ACL FET driver. Connect a bootstrap 4 BOOT_CL UHV (620 V) diode from V5OUT to BOOT_CL and a bootstrap capacitor from SW node 6 GND LV (0) Power ground pin for the IC. Connect to GND 7 V10 LV (10 V) Supply voltage input, 9.5 V nominal 8 GATE LV (10 V) Gate driver output for Primary N-FET (refer to V10) 9 TEMP LV (5 V) External NTC temperature sensor input 10 DGND LV (0) Digital ground. Connect to GND Current sense input. Connect to the positive terminal of the current shunt 11 ISNS LV (5 V) resistor Output voltage error input (feedback). Connect to the Optocoupler collector 12 FB LV (5 V) and pull up to V5OUT 13 V5OUT LV (5 V) Output and decoupling pin for the internal +5 V supply Auxiliary winding sense input for QR operation. Connect the auxiliary positive 14 VAUX_S LV: (10 V) terminal to this pin via a resistor divider VBULK sense input. Connect to the rectified input voltage (VBULK) via a 15 VBULK_S LV: (5 V) resistor divider 16 CLMP_S LV: (5 V) Active Clamp sense input. Connect to CLAMP via a resistive divider Silanna Semiconductor Proprietary and Confidential Page 2 For more information: www.SilannaSemi.com Document 10854 Ver. 3.0