Datasheet HT32F59041 (Holtek) - 7

Enhanced 24-bit A/D Arm® Cortex®-M0+ MCU HT32F59041
2 Features Core
▆ 32-bit Arm® Cortex®-M0+ processor core
1 General Description
▆ Up to 20 MHz operating frequency
2 Features
▆ Single-cycle multiplication ▆ Integrated Nested Vectored Interrupt Controller (NVIC) ▆ 24-bit SysTick timer The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized, low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb® instruction sets, single-cycle I/O port, hardware multiplier and low latency interrupt respond time.
On-chip Memory
▆ 64 KB on-chip Flash memory for instruction/data and options storage ▆ 8 KB on-chip SRAM ▆ Supports multiple boot modes The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external interface to external AHB peripherals. The processor accesses take priority over debug accesses. The maximum address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width. Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce the software complexity of repeated implementation by different device vendors. However, some regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+ Technical Reference Manual for more information. Figure 2 in the Overview chapter shows the memory map of the device, including code, SRAM, peripheral and other pre-defined regions.
Flash Memory Controller – FMC
▆ 32-bit word programming with In System Programming Interface (ISP) and In Application Programming (IAP) ▆ Flash protection capability to prevent illegal access The Flash Memory Controller, FMC, provides all the necessary functions for the embedded on- chip Flash Memory. The word program/page erase functions are also provided. Rev. 1.00 7 of 59 January 17, 2020 Document Outline 1 General Description 2 Features Core On-chip Memory Flash Memory Controller – FMC Reset Control Unit – RSTCU Clock Control Unit – CKCU Power Management Control Unit – PWRCU Real Time Clock – RTC External Interrupt / Event Controller – EXTI Hardware Divider – DIV 12-Bit Analog to Digital Converter – ADC 24-Bit Delta Sigma Analog to Digital Converter – ΔΣ ADC I/O Ports – GPIO Basic Function Timer – BFTM Motor Control Timer – MCTM PWM Generation and Capture Timer – GPTM Pulse Width Modulation – PWM Watchdog Timer – WDT Inter-integrated Circuit – I2C Serial Peripheral Interface – SPI Universal Synchronous Asynchronous Receiver Transmitter – USART Universal Asynchronous Receiver Transmitter – UART Cyclic Redundancy Check – CRC Debug Support Package and Operation Temperature 3 Overview Device Information Block Diagram Memory Map Clock Structure 4 24-Bit Delta Sigma A/D Converter – ΔΣ ADC 24-Bit A/D Converter Internal Registers Internal Power Supply Reference Voltages Power and Reference Control Oscillator Input Signal Gain Control Amplifier – PGA 24-Bit Analog to Digital Converter Operation External Interface Communication 5 Pin Assignment 6 Electrical Characteristics Absolute Maximum Ratings Recommended DC Operating Conditions On-Chip LDO Voltage Regulator Characteristics Power Consumption Reset and Supply Monitor Characteristics External Clock Characteristics Internal Clock Characteristics Memory Characteristics I/O Port Characteristics 12-Bit ADC Characteristics 24-Bit ADC Characteristics Effective Number of Bits (ENOB) MCTM/GPTM/PWM Characteristics I2C Characteristics SPI Characteristics 7 Package Information 48-pin LQFP (7mm × 7mm) Outline Dimensions