Datasheet AD73322L (Analog Devices) - 4

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AD73322L SPECIFICATIONS
AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 8 kHz; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range as follows: A grade, TMIN = −40°C, TMAX = +85°C; Y grade, TMIN = −40°C, TMAX = +105°C.
Table 1. A and Y Versions Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/°C 0.1 µF capacitor required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.08 1.2 1.32 V Unloaded Minimum Load Resistance 1 kΩ Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 1.578 V Max output swing = (1.578/1.2) × VREFCAP Feedback Resistance 50 kΩ fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting −1 Gain Resolution 5 Bits Gain step size = 0.0625 Gain Accuracy ±1.0 % Output unloaded Settling Time 1.0 µs Tap gain change of −FS to +FS Delay 0.5 µs ADC SPECIFICATIONS DAC unloaded Maximum Input Range at VIN1, 2 1.578 V p-p Measured differentially −2.85 dBm Max input = (1.578/1.2) × VREFCAP Nominal Reference Level at VIN 1.0954 V p-p Measured differentially (0 dBm0) −6.02 dBm Absolute Gain PGA = 0 dB −2.0 −0.7 +0.5 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to −50 dBm0 Signal-to-Noise and Distortion Refer to Figure 9 PGA = 0 dB 70 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 0 79 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 1 77.5 dB 0 Hz to fSAMP/2; fSAMP = 8 kHz Total Harmonic Distortion PGA = 0 dB −86 −75 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz Intermodulation Distortion −61 dB PGA = 0 dB Idle Channel Noise Crosstalk −72 dBm0 PGA = 0 dB ADC-to-DAC −107 dB ADC input signal level: 1.0 kHz, 0 dBm0 DAC input at idle ADC-to-ADC −92 dB ADC1 input signal level: 1.0 kHz, 0 dBm0 ADC2 input at idle; input amplifiers bypassed −93 dB Input amplifiers included in input channel DC Offset −20 0 +20 mV PGA = 0 dB Power Supply Rejection Ratio −65 dB Input signal level at AVDD and DVDD pins: 1.0 kHz, 100 mV p-p sine wave Rev. A | Page 4 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE