Datasheet AD73322L (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| Pages / Page | 48 / 10 — AD73322L. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VINP1. 28 VFBN2. … |
| Revision | A |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD73322L. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VINP1. 28 VFBN2. VINP1 1. VFBP1. 27 VINN2. VINN1. 26 VFBP2. VFBP2. VFBN1. 25 VINP2
Model Line for this Datasheet
Text Version of Document
AD73322L PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VINP1 1 28 VFBN2 VINP1 1 28 VFBN2 VFBP1 2 27 VINN2 VFBP1 2 27 VINN2 VINN1 3 26 VFBP2 VINN1 3 26 VFBP2 VFBN1 4 25 VINP2 VFBN1 4 25 VINP2 REFOUT 5 AD73322L 24 VOUTN1 REFOUT 5 AD73322L 24 VOUTN1 TOP VIEW REFCAP 6 23 VOUTP1 TOP VIEW REFCAP 6 23 VOUTP1 (Not to Scale) AVDD2 7 22 VOUTN2 AVDD2 7 22 VOUTN2 AGND2 8 21 VOUTP2 AGND2 8 21 VOUTP2 DGND 9 20 AVDD1 DGND 9 20 AVDD1 DVDD 10 19 AGND1 DVDD 10 19 AGND1 RESET 11 18 SE RESET 11 18 SE SCLK 12 17 SDI SCLK 12 17 SDI MCLK 13 16 SDIFS MCLK 13 16 SDIFS SDO 14 15 SDOFS SDO 14 15 SDOFS
00691-006 00691-007 Figure 6. 28-Lead Wide Body Figure 7. 28-Lead Thin Shrink
1 2 2 P 1 N P 2 BN1 P P F INN1 INN2 NC V V VFB VIN NC VFB V VFB VIN NC 44 43 42 41 40 39 38 37 36 35 34 REFOUT 1 33 NC REFCAP PIN 1 2 32 VOUTN1 AVDD2 3 31 VOUTP1 AVDD2 4 30 NC AGND2 5 29 VOUTN2 AD73322L AGND2 6 28 TOP VIEW VOUTP2 AGND2 7 (Not to Scale) 27 NC AGND2 8 26 AVDD1 DGND 9 25 AVDD1 DGND 10 24 AGND1 DVDD 11 23 AGND1 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT I O NC LK NC IFS SE NC OFS SD ESET SD SC
00691-008
R MCLK SD SD
Figure 8. 44-Lead Plastic Thin Quad Flatpack
Table 6. Pin Function Descriptions Mnemonic Function
VINP1 Analog Input to the inverting input amplifier on Channel 1’s positive input. VFBP1 Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator. VINN1 Analog Input to the inverting input amplifier on Channel 1’s negative input. VFBN1 Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator. REFOUT Buffered Reference Output, which has a nominal value of 1.2 V. REFCAP A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. AVDD2 Analog Power Supply Connection. AGND2 Analog Ground/Substrate Connection2. DGND Digital Ground/Substrate Connection. DVDD Digital Power Supply Connection. RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Rev. A | Page 10 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE
00691-006 00691-007 Figure 6. 28-Lead Wide Body Figure 7. 28-Lead Thin Shrink
1 2 2 P 1 N P 2 BN1 P P F INN1 INN2 NC V V VFB VIN NC VFB V VFB VIN NC 44 43 42 41 40 39 38 37 36 35 34 REFOUT 1 33 NC REFCAP PIN 1 2 32 VOUTN1 AVDD2 3 31 VOUTP1 AVDD2 4 30 NC AGND2 5 29 VOUTN2 AD73322L AGND2 6 28 TOP VIEW VOUTP2 AGND2 7 (Not to Scale) 27 NC AGND2 8 26 AVDD1 DGND 9 25 AVDD1 DGND 10 24 AGND1 DVDD 11 23 AGND1 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT I O NC LK NC IFS SE NC OFS SD ESET SD SC
00691-008
R MCLK SD SD
Figure 8. 44-Lead Plastic Thin Quad Flatpack
Table 6. Pin Function Descriptions Mnemonic Function
VINP1 Analog Input to the inverting input amplifier on Channel 1’s positive input. VFBP1 Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator. VINN1 Analog Input to the inverting input amplifier on Channel 1’s negative input. VFBN1 Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator. REFOUT Buffered Reference Output, which has a nominal value of 1.2 V. REFCAP A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. AVDD2 Analog Power Supply Connection. AGND2 Analog Ground/Substrate Connection2. DGND Digital Ground/Substrate Connection. DVDD Digital Power Supply Connection. RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Rev. A | Page 10 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE
