Datasheet PI6CB33402 (Diodes) - 3
| Manufacturer | Diodes |
| Description | Very Low Power 4-Output PCIe Clock Buffer With On-Chip Termination |
| Pages / Page | 20 / 3 — PI6CB33402. Pin Description Cont. Pin Number Pin Name. Type. Description |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
PI6CB33402. Pin Description Cont. Pin Number Pin Name. Type. Description
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A product Line of Diodes Incorporated
PI6CB33402 Pin Description Cont. Pin Number Pin Name Type Description
19 OE1# Input CMOS Active low input for enabling Q1 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 20 NC Do not connect this pin 21 VDDA Power Power supply for analog circuitry 22 Q2+ Output HCSL Differential true clock output 23 Q2- Output HCSL Differential complementary clock output 24 OE2# Input CMOS Active low input for enabling Q2 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 26 NC Do not connect this pin 27 Q3+ Output HCSL Differential true clock output 28 Q3- Output HCSL Differential complementary clock output 29 OE3# Input CMOS Active low input for enabling Q3 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 30 NC Do not connect this pin Input notifies device to sample latched inputs and start up on first high 31 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 32 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down EPAD Power Connect to Ground PI6CB33402 www.diodes.com January 2020 Document Number DS41293 Rev 5-2 3 Diodes Incorporated
PI6CB33402 Pin Description Cont. Pin Number Pin Name Type Description
19 OE1# Input CMOS Active low input for enabling Q1 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 20 NC Do not connect this pin 21 VDDA Power Power supply for analog circuitry 22 Q2+ Output HCSL Differential true clock output 23 Q2- Output HCSL Differential complementary clock output 24 OE2# Input CMOS Active low input for enabling Q2 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 26 NC Do not connect this pin 27 Q3+ Output HCSL Differential true clock output 28 Q3- Output HCSL Differential complementary clock output 29 OE3# Input CMOS Active low input for enabling Q3 pair. This pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 30 NC Do not connect this pin Input notifies device to sample latched inputs and start up on first high 31 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 32 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down EPAD Power Connect to Ground PI6CB33402 www.diodes.com January 2020 Document Number DS41293 Rev 5-2 3 Diodes Incorporated
