Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 12

PRELIMINARY EZ-PD CCG6DF, CCG6SF Table 3. Pinout for CYPD6127-96BZXI Group Name Pin Name Port Pin Description
CC1 Analog B3 USB PD connector detect/Configuration Channel 1 USB Type-C CC2 Analog B5 USB PD connector detect/Configuration Channel 2 DP_SYS Analog K11 USB 2.0 DP from the Host System DM_SYS Analog J11 USB 2.0 DM from the Host System UART_TX/P1.4 GPIO H10 UART Tx from Host System/GPIO UART_RX/P1.3 GPIO G10 UART Rx from Host System/GPIO DP_BOT Analog K10 USB 2.0 DP from Bottom of Type-C Connector DM_BOT Analog J10 USB 2.0 DM from Bottom of Type-C Connector Muxes/Switches DM_TOP Analog H11 USB 2.0 DM from Top of Type-C Connector DP_TOP Analog G11 USB 2.0 DP from Top of Type-C Connector SBU2 Analog A4 Type-C Sideband Use signal – Connector side SBU1 Analog A5 Type-C Sideband Use signal – Connector side SBU1_SYS Analog B6 Type-C Sideband Use signal – System side SBU2_SYS Analog A6 Type-C Sideband Use signal – System side VBUS Control VBUS_C_CTRL Analog A3 Full rail control I/O for enabling/disabling Consumer load NFET of USB Type-C CSP Analog A11 Current Sense Positive Input for VBUS side external Rsense VBUS OCP CSN Analog A10 Current Sense Negative input for other side of external Rsense I2C_SDA_SCB1/P0.2 GPIO K9 SCB1 data for communicating with SoC or TBT controller/ GPIO I2C_SCL_SCB1/P0.3 GPIO H7 SCB1 clock for communicating with SoC or TBT controller / GPIO I2C_INT_EC/P1.2 GPIO F11 Embedded Controller interrupt / GPIO I2C_INT_TBT/P0.4 GPIO L9 ThunderBolt interrupt / GPIO SWD_IO/P1.1 GPIO G8 Serial Wire Debug I/O / GPIO SWD_CLK/P1.0 GPIO F10 Serial Wire Debug Clock / GPIO HPD/P2.0 GPIO F8 Hot Plug Detect I/O / GPIO I2C_SDA_SCB2/P2.1 GPIO E11 SCB2 data for configuring Re-timer or DP/USB GPIOs and Serial Multi-Function MUX/ GPIO Interfaces I2C_SCL_SCB2/P2.2 GPIO E10 SCB2 clock for configuring Re-timer or DP/USB Multi-Function MUX/ GPIO P2.3 GPIO E8 GPIO P2.4 GPIO D10 GPIO P2.5 GPIO D8 GPIO I2C_SCL_SCB0/P4.0 GPIO D11 SCB0 clock for communicating with Embedded controller / GPIO I2C_SDA_SCB0/P4.1 GPIO C11 SCB0 data for communicating with Embedded controller / GPIO P3.0 GPIO B10 GPIO I2C_SDA_SCB3/P3.1 GPIO B11 SCB3 data / GPIO Document Number: 002-27161 Rev. *E Page 12 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support